ViewSonic VP150M Service Manual - Page 42

Vsync/cvsync

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ViewSonic September 2000 - Version 1.0 THEORY OF CIRCUIT OPERATION Service Manual VP150m The SYNC processing block performs the functions of composite signal separation, sync inputs presence check, frequency counting, polarity detection and control, as well as protection of VBLANK output while VSYNC speed up in high DDC communication clock rate. The preset and frequency function block treat any pulse shorter than one OSC period as noise. Composite sync separate MTV112E continuously monitors the input HSYNC, if the vertical sync pulse can be extracted from the input, a CVpre flag is set and user can select the extracted "CVSYNC" for the source of polarity check, frequency count, and VBLANK. The CVSYNC will have 10-16 us delay compared to the original signal. The delay depends on the OSC frequency and composite mix method. HN Polarity Detect The polarity functions detect the input HSYNC/VSYNC high and low pules duty cycle. If the high pules duration is longer than that of low pulse, the negative polarity is asserted; otherwise positive polarity is asserted. The HPLchg interrupt is set when the Hpol value changes. The VPLchg interrupt is set when Vpol value changes. HN Frequency Counter MTV112E can discriminate HSYNC/VSYNC frequency and saves the information in XFRs. The 15 bits Hcounter counts the time of 64XHSYNC period, but only 11 upper bits are loaded into the HCNTH/HCNTL latch. The 11 bits output value will be (2/Hfreq) / (1/OSCfreq), updated once per VSYNC/CVSYNC period when VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC is non-present. The 14 bits Vcounter counts the time between two VSYNC pules, but only 9 upper bits are loaded into the VCNTHNCNTL latch. The 9 bits output value will be (1Nfreq) / (512/OSCfreq), updated every VSYNC/CVSYNC period. An extra overflow it indicates the condition of HN counter overflow. The VFchg/HFchg interrupt is active when VCNT/HCNT value changes or overflow. Confidential - Do Not Copy Page 41

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ViewSonic
September
2000
-
Version
1.0
Service
Manual
VP150m
THEORY
OF
CIRCUIT
OPERATION
The
SYNC
processing
block
performs
the
functions
of
composite
signal
separation,
sync
inputs
presence
check,
frequency
counting,
polarity
detection
and
control,
as
well
as
protection
of
VBLANK
output
while
VSYNC
speed
up
in
high
DDC
communication
clock
rate.
The
preset
and
frequency
function
block
treat
any
pulse
shorter
than
one
OSC
period
as
noise.
Composite
sync
separate
MTV112E
continuously
monitors
the
input
HSYNC,
if
the
vertical
sync
pulse
can
be
extracted
from
the
input,
a
CVpre
flag
is
set
and
user
can
select
the
extracted
"CVSYNC"
for
the
source
of
polarity
check,
frequency
count,
and
VBLANK.
The
CVSYNC
will
have
10-16
us
delay
compared
to
the
original
signal.
The
delay
depends
on
the
OSC
frequency
and
composite
mix
method.
HN
Polarity
Detect
The
polarity
functions
detect
the
input
HSYNC/VSYNC
high
and
low
pules
duty
cycle.
If
the
high
pules
duration
is
longer
than
that
of
low
pulse,
the
negative
polarity
is
asserted;
otherwise
positive
polarity
is
asserted.
The
HPLchg
interrupt
is
set
when
the
Hpol
value
changes.
The
VPLchg
interrupt
is
set
when
Vpol
value
changes.
HN
Frequency
Counter
MTV112E
can
discriminate
HSYNC/VSYNC
frequency
and
saves
the
information
in
XFRs.
The
15
bits
Hcounter
counts
the
time
of
64XHSYNC
period,
but
only
11
upper
bits
are
loaded
into
the
HCNTH/HCNTL
latch.
The
11
bits
output
value
will
be
(2/Hfreq)
/
(1/OSCfreq),
updated
once
per
VSYNC/CVSYNC
period
when
VSYNC/CVSYNC
is
present
or
continuously
updated
when
VSYNC/CVSYNC
is
non
-present.
The
14
bits
Vcounter
counts
the
time
between
two
VSYNC
pules,
but
only
9
upper
bits
are
loaded
into
the
VCNTHNCNTL
latch.
The
9
bits
output
value
will
be
(1Nfreq)
/
(512/OSCfreq),
updated
every
VSYNC/CVSYNC
period.
An
extra
overflow
it
indicates
the
condition
of
HN
counter
overflow.
The
VFchg/HFchg
interrupt
is
active
when
VCNT/HCNT
value
changes
or
overflow.
Confidential
—
Do
Not
Copy
Page
41