ViewSonic VP150M Service Manual - Page 36

ViewSonic, Service, Manual, THEORY, CIRCUIT, OPERATION

Page 36 highlights

ViewSonic September 2000 - Version 1.0 THEORY OF CIRCUIT OPERATION Service Manual VP150m The detection logic is always active to automatically detect any changes to the input Mode. Users can manually change the input mode information at run time through the CPU interface. Detailed operation of the CPU interface is described in Section 3.6 of "CPU Interface". Mode detection and frequency detection can be independently turned ON or OFF by the external CPU. This feature allows system customers to have better control of the mode-detection and frequency detection process. When the detection is turned OFF, the external CPU can change the input mode and frequency definitions. Phase calibration The AM101-1 can automatically calibrate the phase of the sample clock in order to preserve the bandwidth of the input signal and to get the best quality. The AM1011 implements a proprietary image quality function. During the auto-calibration process, the AM101-1 continues to search for the best phase to optimize the image quality. The output image may display some jitter and blurring during the auto-calibration process, and the image will become crisp and sharp once the optimum phase is found. User can change the sampling clock phase value through the external CPU. Detailed operation of the CPU interface is described in Section 3.6 of "CPU Interface". The phase calibration process can be delayed and even disabled by the external CPU if the system designer wants to have his/her own implementation. The phase calibration can be independently turned ON or OFF by the external CPU. PWM operation The AM101-1 implements a unique algorithm to adjust the phase of the AID converter's sampling clock. An external delay circuit is required to compliment the AM101-1 for the phase-calibration process. The AM101-1 generates a PulseWidth Modulated (PWM) signal to the external delay circuit. The delay circuit should insert a certain amount of time delay synchronization pulse based upon the width of the PWM signal. Confidential - Do Not Copy Page 35

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ViewSonic
September
2000
-
Version
1.0
Service
Manual
VP150m
THEORY
OF
CIRCUIT
OPERATION
The
detection
logic
is
always
active
to
automatically
detect
any
changes
to
the
input
Mode.
Users
can
manually
change
the
input
mode
information
at
run
time
through
the
CPU
interface.
Detailed
operation
of
the
CPU
interface
is
described
in
Section
3.6
of
"CPU
Interface".
Mode
detection
and
frequency
detection
can
be
independently
turned
ON
or
OFF
by
the
external
CPU.
This
feature
allows
system
customers
to
have
better
control
of
the
mode
-detection
and
frequency
detection
process.
When
the
detection
is
turned
OFF,
the
external
CPU
can
change
the
input
mode
and
frequency
definitions.
Phase
calibration
The
AM101-1
can
automatically
calibrate
the
phase
of
the
sample
clock
in
order
to
preserve
the
bandwidth
of
the
input
signal
and
to
get
the
best
quality.
The
AM101-
1
implements
a
proprietary
image
quality
function.
During
the
auto
-calibration
process,
the
AM101-1
continues
to
search
for
the
best
phase
to
optimize
the
image
quality.
The
output
image
may
display
some
jitter
and
blurring
during
the
auto
-calibration
process,
and
the
image
will
become
crisp
and
sharp
once
the
optimum
phase
is
found.
User
can
change
the
sampling
clock
phase
value
through
the
external
CPU.
Detailed
operation
of
the
CPU
interface
is
described
in
Section
3.6
of
"CPU
Interface".
The
phase
calibration
process
can
be
delayed
and
even
disabled
by
the
external
CPU
if
the
system
designer
wants
to
have
his/her
own
implementation.
The
phase
calibration
can
be
independently
turned
ON
or
OFF
by
the
external
CPU.
PWM
operation
The
AM101-1
implements
a
unique
algorithm
to
adjust
the
phase
of
the
AID
converter's
sampling
clock.
An
external
delay
circuit
is
required
to
compliment
the
AM101-1
for
the
phase
-calibration
process.
The
AM101-1
generates
a
Pulse
-
Width
Modulated
(PWM)
signal
to
the
external
delay
circuit.
The
delay
circuit
should
insert
a
certain
amount
of
time
delay
synchronization
pulse
based
upon
the
width
of
the
PWM
signal.
Confidential
Do
Not
Copy
Page
35