ViewSonic VP150M Service Manual - Page 30

ViewSonic VP150M - 15" LCD Monitor Manual

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ViewSonic September 2000 - Version 1.0 THEORY OF CIRCUIT OPERATION Pin Description Service Manual VP150m Symbol B_IN10 B_IN11 B_IN12 B_IN13 DATA_SEL B_IN14 B_IN15 B_IN16 B_IN17 ROM_SCL ROM SDA GND CPU_SCL CPU SDA PWM_CTL CLK_1M VDD CLK_1M_O RESET_B R_OSD G_OSD B_OSD EN_OSD SCAN_EN TEST_EN VCLK01 FCLKO VCLK00 FCLK1 VCLK1 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 I/O Description I Channel B Data Input Color Blue (LSB) I Channel B Data Input Color Blue I Channel B Data Input Color Blue I Channel B Data Input Color Blue I Indicate Channel A or Channel B contains valid input data: 1: data in Channel A is valid 0: data in Channel B is valid I Channel B Data Input Color Blue I Channel B Data Input Color Blue I Channel B Data Input Color Blue I Channel B Data Input Color Blue (MSB) 0 SCL in I2C for EEPROM interface I/O SDA in I2C for EEPROM interface Ground I SCL in I2C for CPU interface I/O SDA in I2C for CPU interface 0 PWM control signal (Detail description in PWM Operation Section) I Free Running Clock (default: MHz) Power Supply 0 Feedback of free Running Clock I System Reset (active LOW) I OSD Color Red I OSD Color Green I OSD Color Blue I OSD Mixer Enable =0, No OSD output =1, R_OUT[7:0]={R_OSD repeat 8 times} G_OUT[7:0]={G_OSD repeat 8 times} B_OUT[7:0]={B_OSD repeat 8 times} I Manufacturing test pin (NC) I Manufacturing test pin (NC) I Input Clock 1 0 Input PLL Feedback Clock I Input Clock 0 0 Output PLL Feedback Clock I Output PLL Output Clock Confidential - Do Not Copy Page 29

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ViewSonic
September
2000
-
Version
1.0
Service
Manual
VP150m
THEORY
OF
CIRCUIT
OPERATION
Pin
Description
Symbol
Pin
Number
I/O
Description
B_IN10
1
I
Channel
B
Data
Input
Color
Blue
(LSB)
B_IN11
2
I
Channel
B
Data
Input
Color
Blue
B_IN12
3
I
Channel
B
Data
Input
Color
Blue
B_IN13
4
I
Channel
B
Data
Input
Color
Blue
DATA_SEL
5
I
Indicate
Channel
A
or
Channel
B
contains
valid
input
data:
1:
data
in
Channel
A
is
valid
0:
data
in
Channel
B
is
valid
B_IN14
6
I
Channel
B
Data
Input
Color
Blue
B_IN15
7
I
Channel
B
Data
Input
Color
Blue
B_IN16
8
I
Channel
B
Data
Input
Color
Blue
B_IN17
9
I
Channel
B
Data
Input
Color
Blue
(MSB)
ROM_SCL
10
0
SCL
in
I
2
C
for
EEPROM
interface
ROM
SDA
11
I/O
SDA
in
I
2
C
for
EEPROM
interface
GND
12
Ground
CPU_SCL
13
I
SCL
in
I
2
C
for
CPU
interface
CPU
SDA
14
I/O
SDA
in
I
2
C
for
CPU
interface
PWM_CTL
15
0
PWM
control
signal
(Detail
description
in
PWM
Operation
Section)
CLK_1M
16
I
Free
Running
Clock
(default:
MHz)
VDD
17
Power
Supply
CLK_1M_O
18
0
Feedback
of
free
Running
Clock
RESET_B
19
I
System
Reset
(active
LOW)
R_OSD
20
I
OSD
Color
Red
G_OSD
21
I
OSD
Color
Green
B_OSD
22
I
OSD
Color
Blue
EN_OSD
23
I
OSD
Mixer
Enable
=0,
No
OSD
output
=1,
R_OUT[7:0]={R_OSD
repeat
8
times}
G_OUT[7:0]={G_OSD
repeat
8
times}
B_OUT[7:0]={B_OSD
repeat
8
times}
SCAN_EN
24
I
Manufacturing
test
pin
(NC)
TEST_EN
25
I
Manufacturing
test
pin
(NC)
VCLK01
26
I
Input
Clock
1
FCLKO
27
0
Input
PLL
Feedback
Clock
VCLK00
28
I
Input
Clock
0
FCLK1
29
0
Output
PLL
Feedback
Clock
VCLK1
30
I
Output
PLL
Output
Clock
Confidential
—
Do
Not
Copy
Page
29