ViewSonic VP150M Service Manual - Page 26

ViewSonic VP150M - 15" LCD Monitor Manual

Get ViewSonic VP150M - 15inch LCD Monitor PDF manuals and user guides
UPC - 766907700619
View all ViewSonic VP150M manuals
Add to My Manuals
Save this manual to your list of manuals

Page 26 highlights

ViewSonic September 2000 - Version 1.0 THEORY OF CIRCUIT OPERATION Service Manual VP150m Clamp, Video Amplifier, and Analog-to-Digital Circuits Clamp Circuits (Adjust RGB Inputs to ADC Range) For an ICS1531 chip to properly digitize the incoming RGB analog signals, the ICS1531 must adjust the signals to the range of the ADC. This adjustment is done by clamping the signal, which both, (1) establishes a bottom limit, and (2) offsets the signal to align the black level of the incoming signal with the bottom limit. Then the signal is amplified to adjust the top limit to the upper range of the ADC. The ICS1531 incorporates an internal clamping circuit to generate a clamping signal. Optionally, the CLAMP pin can be used to input an externally generated clamp signal. Typically, the clamp signal is generated by ADCSYNC (which provides the recovered HSYNC timing pulse). The clamp signal is generated during a nondisplay region of time, when most PC display controllers output a black signal. Video Amplifier Circuits (Amplify RGB Inputs) The ICS1531 can directly accept analog RGB input signals from a PC display controller (that is, no external pre-amplifier is required). The video amplifier circuit has three independent 500-MHz video amplifiers for the RGB inputs. To adjust the top level of the signal, this video amplifier circuit can be programmed for a gain of 1.0, 1.2, 1.4, or 1.6. As a result, the video amplifier circuit can improve weak signals and adjust analog input signals for the optimum sampling range of the ADC circuit. Analog-to-Digital Circuits (Digitize RGB Inputs) The ICS1531 has high-performance analog-to-digital converters (ADCs) to capture and digitize analog RGB data. Low-power CMOS technology is used to create 8-bit ADCs, which are calibrated to align the capture event between the 3 analog input channels and 6 digital output channels. The ADC can provide one of the following: Two 24-bit pixels aligned to a half-rate pixel clock (two-pixels-per-clock mode), which can be used for 48-bit interface panels and image-scaling chips One 24-bit pixel aligned to a full-rate pixel clock (one-pixel-per-clock mode), which can be used for full-scale 8-bit sampling that allows accurate image representation in up to 24-bit-per-pixel applications In addition, programmable digital-to-analog converters for the R, G, and B inputs fine-tune the Individual R, G, and B maximum reference lop' voltages (VRTR, VRTG, and VRTB). Confidential - Do Not Copy Page 25

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
ViewSonic
September
2000
-
Version
1.0
Service
Manual
VP150m
THEORY
OF
CIRCUIT
OPERATION
Clamp,
Video
Amplifier,
and
Analog
-to
-Digital
Circuits
Clamp
Circuits
(Adjust
RGB
Inputs
to
ADC
Range)
For
an
ICS1531
chip
to
properly
digitize
the
incoming
RGB
analog
signals,
the
ICS1531
must
adjust
the
signals
to
the
range
of
the
ADC.
This
adjustment
is
done
by
clamping
the
signal,
which
both,
(1)
establishes
a
bottom
limit,
and
(2)
offsets
the
signal
to
align
the
black
level
of
the
incoming
signal
with
the
bottom
limit.
Then
the
signal
is
amplified
to
adjust
the
top
limit
to
the
upper
range
of
the
ADC.
The
ICS1531
incorporates
an
internal
clamping
circuit
to
generate
a
clamping
signal.
Optionally,
the
CLAMP
pin
can
be
used
to
input
an
externally
generated
clamp
signal.
Typically,
the
clamp
signal
is
generated
by
ADCSYNC
(which
provides
the
recovered
HSYNC
timing
pulse).
The
clamp
signal
is
generated
during
a
non
-
display
region
of
time,
when
most
PC
display
controllers
output
a
black
signal.
Video
Amplifier
Circuits
(Amplify
RGB
Inputs)
The
ICS1531
can
directly
accept
analog
RGB
input
signals
from
a
PC
display
controller
(that
is,
no
external
pre
-amplifier
is
required).
The
video
amplifier
circuit
has
three
independent
500
-MHz
video
amplifiers
for
the
RGB
inputs.
To
adjust
the
top
level
of
the
signal,
this
video
amplifier
circuit
can
be
programmed
for
a
gain
of
1.0, 1.2,
1.4,
or
1.6.
As
a
result,
the
video
amplifier
circuit
can
improve
weak
signals
and
adjust
analog
input
signals
for
the
optimum
sampling
range
of
the
ADC
circuit.
Analog
-to
-Digital
Circuits
(Digitize
RGB
Inputs)
The
ICS1531
has
high-performance
analog
-to
-digital
converters
(ADCs)
to
capture
and
digitize
analog
RGB
data.
Low
-power
CMOS
technology
is
used
to
create
8
-bit
ADCs,
which
are
calibrated
to
align
the
capture
event
between
the
3
analog
input
channels
and
6
digital
output
channels.
The
ADC
can
provide
one
of
the
following:
Two
24
-bit
pixels
aligned
to
a
half
-rate
pixel
clock
(two
-pixels
-per
-clock
mode),
which
can
be
used
for
48
-bit
interface
panels
and
image
-scaling
chips
One
24
-bit
pixel
aligned
to
a
full
-rate
pixel
clock
(one
-pixel
-per
-clock
mode),
which
can
be
used
for
full-scale
8
-bit
sampling
that
allows
accurate
image
representation
in
up
to
24
-bit
-per
-pixel
applications
In
addition,
programmable
digital
-to
-analog
converters
for
the
R,
G,
and
B
inputs
fine-tune
the
Individual
R,
G,
and
B
maximum
reference
lop'
voltages
(VRTR,
VRTG,
and
VRTB).
Confidential
—
Do
Not
Copy
Page
25