ViewSonic VP150M Service Manual - Page 21

Power, Management, Description, Differential, Signal

Page 21 highlights

Service Manual VP150m THEORY OF CIRCUIT OPERATION ViewSonic September 2000 - Version 1.0 Power Management Pins Description Pin Pin # Type Name Description SCDT 8 Out Sync Detect. A HIGH level is outputted when DE is actively toggling indicating that the link is alive. A LOW level is outputted when DE is inactive, indicating the link is down. Can be connected to PDO to power down the outputs when DE is not detected. The SCDT output itself, however, Remains in the active mode at all times. PDO 9 In Output Driver Power Down (active LOW). A HIGH level indicates normal operation. A LOW level puts all the output drivers only (except SCDT and CTL1) into a high impedance (tri-stats) mode. A weak internal pull-down device brings each output to ground. PDO is a sub-set of the PD description. The chip is not in power-down mode with this pin. There is an internal pull-up resistor that defaults the chip to normal operation if left unconnected. SCDT and CTL1 are not tri-stated by this pin. PD 2 In Power Down (active LOW). A HIGH level indicates normal operation and a LOW level indicates power down mode. During power down mode, all output buffers are disabled and brought low, all analog logic is powered down, and all inputs are disabled. Differential Signal Data Pins Description Pin Pin # Type Name Description RXO+ 90 Analog TMDS Low Voltage differential Signal input data pairs. RX0- 91 Analog RX1+ 85 Analog RX1- 86 Analog RX2+ 80 Analog RX2- 81 Analog RXC+ 93 Analog TMDS Low Voltage differential Signal input data pairs. RXC- 94 Analog PDO 9 In Impedance Matching Control. Resistor value should be ten times the characteristic impedance of the cable. In the common case of 50 transmission line, an external 500 resistor must be connected between AVCC and this pin. Page 20 Confidential - Do Not Copy

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Service
Manual
VP150m
ViewSonic
September
2000
-
Version
1.0
THEORY
OF
CIRCUIT
OPERATION
Power
Management
Pins
Description
Pin
Name
Pin
#
Type
Description
SCDT
8
Out
Sync
Detect.
A
HIGH
level
is
outputted
when
DE
is
actively
toggling
indicating
that
the
link
is
alive.
A
LOW
level
is
outputted
when
DE
is
inactive,
indicating
the
link
is
down.
Can
be
connected
to
PDO
to
power
down
the
outputs
when
DE
is
not
detected.
The
SCDT
output
itself,
however,
Remains
in
the
active
mode
at
all
times.
PDO
9
In
Output
Driver
Power
Down
(active
LOW).
A
HIGH
level
indicates
normal
operation.
A
LOW
level
puts
all
the
output
drivers
only
(except
SCDT
and
CTL1)
into
a
high
impedance
(tri-stats)
mode.
A
weak
internal
pull
-down
device
brings
each
output
to
ground.
PDO
is
a
sub
-set
of
the
PD
description.
The
chip
is
not
in
power
-down
mode
with
this
pin.
There
is
an
internal
pull-up
resistor
that
defaults
the
chip
to
normal
operation
if
left
unconnected.
SCDT
and
CTL1
are
not
tri-stated
by
this
pin.
PD
2
In
Power
Down
(active
LOW).
A
HIGH
level
indicates
normal
operation
and
a
LOW
level
indicates
power
down
mode.
During
power
down
mode,
all
output
buffers
are
disabled
and
brought
low,
all
analog
logic
is
powered
down,
and
all
inputs
are
disabled.
Differential
Signal
Data
Pins
Description
Pin
Name
Pin
#
Type
Description
RXO+
90
Analog
TMDS
Low
Voltage
differential
Signal
input
data
pairs.
RX0-
91
Analog
RX1+
85
Analog
RX1-
86
Analog
RX2+
80
Analog
RX2-
81
Analog
RXC+
93
Analog
TMDS
Low
Voltage
differential
Signal
input
data
pairs.
RXC-
94
Analog
PDO
9
In
Impedance
Matching
Control.
Resistor
value
should
be
ten
times
the
characteristic
impedance
of
the
cable.
In
the
common
case
of
50
transmission
line,
an
external
500
resistor
must
be
connected
between
AVCC
and
this
pin.
Page
20
Confidential
Do
Not
Copy