ViewSonic VP150M Service Manual - Page 27

Service Manual VP150m THEORY OF CIRCUIT OPERATION ViewSonic September 2000 - Version 1.0 Phase-Locked Loop (Generates Pixel Clock from Input HSYNC) The HSYNC signal to the phase-locked loop (PLL) typically comes from the HSYNC of a PC display controller. This HSYNC signal can have a transition time of tens of nanoseconds. Furthermore, if the HSYNC signal is from a remote source, its pulses can degrade. Schmitt Trigger To condition this HSYNC signal before it inputs to the PLL, a high-performance Schmitt trigger sharpens HSYNC, after which the polarity can be programmed. The result of this conditioning is REF, a clean reference clock signal that, in comparison to the HSYNC signal, has a short transition time. Phase/Frequency Detector The Phase/Frequency Detector (PFD) compares REF (the HSYNC reference signal) and the divided clock output and then drives a charge pump. The PFD gain is programmable over a 7-bit range. Loop Filter The ICS1531 can use either an external or internal loop filter. The advantage of the internal filter is that it can be used for all VESA modes. Voltage-Controlled Oscillator The voltage-controlled oscillator (VCO) operates up to 600MHz with a fixed gain. The Post-Scaler Divider can set the ratio of VCO frequency-to-pixel clock frequency at 2:1, 4:1, 8:1, or 16:1. The maximum pixel clock output frequency is therefore 300 MHz. However, for practical applications, the analog-to-digital converter limits this output frequency to 100 MHz. Analog-to-Digital Converter By using the on-chip 3-channel analog-to-digital converter (ADC), the ICS1531 internally provides the pixel clock needed to synchronize data capture. The pixel clock can be further processed by the Dynamic Phase Adjust. (For more information) on the ADC, "Analog-to-Digital Circuits (Digitize RGB Inputs)". Page 26 Confidential - Do Not Copy