ViewSonic VP150M Service Manual - Page 39

P3./P3.1

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Service Manual VP150m THEORY OF CIRCUIT OPERATION ViewSonic September 2000 - Version 1.0 The MTV112E micro-controller is an 8051 CPU core embedded device specially tailored to CRT display applications. It includes an 8051 CPU core, 256 bytes SRAM, fourteen built-in PWM DACs, DDC2B interface, 24Cxx series EEPROM interface, A/D converter and a 32K bytes internal program EPROM. > P1.0-7 O4- X1 8051 X2 CORE P0.0-7 RD WR INT1 4 P2.0-3 RST 4 P3.0-P3.2 P3.4 P2.4-7 < P0.0.7 > ► RD ► WR XFR WATCH -DOG TIMER RST HSYNC H/VSYNC VSYNC 4 0 CONTROL HBLANK 1.0 ► VBLANK 14 CHANNEL DA0-9 PWM DAC DA10.13 c: .HSCL HSDA DDC 2 B & FIFO INTERFACE • ISCL IIC INTERFACE ISDA P.O FUNCTIONAL DESCRIPTIONS 8051 CPU Core 1. MTV112E includes all the 8051 functions with the following exceptions, PSEN, ALE, RD and WR pins are disabled. The external RAM access is restricted to XFRs within the MTV112E. 2. Port0, port3.3, and port3.5 port3.7 are not general-purpose I/O ports. They are dedicated to display control or DAC pins. 3. INT1 and T1 input pins are not provided. 4. Port2.4 port2.7 are shared with DAC pins; port3.0 port3.2 port3.4 are shared with display control pins. In addition, there are 2 timers, 5 interrupt sources and serial interface compatible with the standard 8051. The Txd/Rxd (P3./P3.1) pins are shared with DDC interface. INTO/TO pins are shared with I2C interface. An extra option can be used to switch the INTO source from P3.2 to P2.0. This feature maintains an external interrupt source when I2C interface Page 38 Confidential - Do Not Copy

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Service
Manual
VP150m
ViewSonic
September
2000
-
Version
1.0
THEORY
OF
CIRCUIT
OPERATION
The
MTV112E
micro
-controller
is
an
8051
CPU
core
embedded
device
specially
tailored
to
CRT
display
applications.
It
includes
an
8051
CPU
core,
256
bytes
SRAM,
fourteen
built-in
PWM
DACs,
DDC2B
interface,
24Cxx
series
EEPROM
interface,
A/D
converter
and
a
32K
bytes
internal
program
EPROM.
P0.0-7
>
P1.0-7
RD
X1
WR
8051
CORE
O4-
X2
INT1
4
P2.0-3
RST
4
P3.0
-P3.2
P3.4
P2.4-7
<
>
►
►
P0.0.7
RD
XFR
WR
WATCH
-DOG
TIMER
RST
c:
.
HSCL
HSDA
DDC
2
B
&
FIFO
INTERFACE
FUNCTIONAL
DESCRIPTIONS
8051
CPU
Core
►
H/VSYNC
HSYNC
VSYNC
CONTROL
HBLANK
VBLANK
4
0
1.0
14
CHANNEL
DA0-9
PWM
DAC
DA10.13
•
IIC
INTERFACE
ISCL
ISDA
P.O
1.
MTV112E
includes
all
the
8051
functions
with
the
following
exceptions,
PSEN,
ALE,
RD
and
WR
pins
are
disabled.
The
external
RAM
access
is
restricted
to
XFRs
within
the
MTV112E.
2.
Port0,
port3.3,
and
port3.5
port3.7
are
not
general-purpose
I/O
ports.
They
are
dedicated
to
display
control
or
DAC
pins.
3.
INT1
and
T1
input
pins
are
not
provided.
4.
Port2.4
port2.7
are
shared
with
DAC
pins;
port3.0
port3.2
port3.4
are
shared
with
display
control
pins.
In
addition,
there
are
2
timers,
5
interrupt
sources
and
serial
interface
compatible
with
the
standard
8051.
The
Txd/Rxd
(P3./P3.1)
pins
are
shared
with
DDC
interface.
INTO/TO
pins
are
shared
with
I
2
C
interface.
An
extra
option
can
be
used
to
switch
the
INTO
source
from
P3.2
to
P2.0.
This
feature
maintains
an
external
interrupt
source
when
I
2
C
interface
Page
38
Confidential
—
Do
Not
Copy