ViewSonic VP150M Service Manual - Page 25

Service Manual VP150m THEORY OF CIRCUIT OPERATION ViewSonic September 2000 - Version 1.0 General Description The ICS1531-100 is a high-performance, cost-effective, 3-channel, 8-bit analog-todigital converter with an integrated line-locked clock generator. This chip is part of a family of chips intended for high-resolution video applications that use analog inputs, such as LCD displays. Using ICS advanced low-voltage CMOS mixedsignal technology, the ICS1531 chips are an effective Data-capture solution for resolutions from VGA to XGA. The ICS1531 chips offer analog-to-digital data conversion and synchronized pixel clock generation up to 100 Mega Samples Per Second (MSPS) or 100 MHz. Dynamic Phase Adjust (DPA) circuitry allows enduser to control the pixel clock phase, relative to the recovered sync signal and analog pixel data. Either the internal pixel clock can be used as a capture clock input to the analog-to-digital converters or an external clock input can be used. The ICS1531 chips provide either one or two pixels per clock. The ADCSYNC output pin provides recovered HSYNC from the pixel clock Phase-Locked-Loop (PLL) divider chain output, which can be used to synchronize display enable output. A clamp signal can be generated internally or provided through the CLAMP pin. A high-bandwidth video amplifier with adjustable gain allows fine tuning of the analog signal. The advanced PLL uses an internal programmable feedback divider. Two additional, independent programmable PLLs, each with spread-spectrum functionality, support memory and panel clock requirements. Functional Block Diagram Red lipLCLAMP Green CLAMP Blue CLAMP VSync .0- HSync SDA 4 SCL XTAL In XTAL Out 4 PLL Serial IF Cystal Oscillator DPA POR RAD-RA7 ADC RBO-RB7 ) GAO-GA7 ADC GBO-GB7 BAO BA7 ADC --) BBO BB7 ADORCLE ADCSYNC ) REF PLL Spead Spectrum ) MOLE PLL Speed Spectrum ) PNLCLK Page 24 Confidential - Do Not Copy