AMD 3200 Revision History

AMD 3200 - Athlon 64 2.0 GHz Processor Manual

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  • AMD 3200 | Revision History - Page 1
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors Publication # 48063 Revision: 3.18 Issue Date: October 2012 Advanced Micro Devices
  • AMD 3200 | Revision History - Page 2
    intended to support or sustain life, or in any other application in which the failure of AMD's product could without notice. Trademarks AMD, the AMD Arrow logo, AMD FX, AMD Opteron, and combinations thereof, of AMD concerning such products or this documentation, for any interruption of service, loss
  • AMD 3200 | Revision History - Page 3
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors List of Figures Figure 1. Format of CPUID Fn0000_0001_EAX...9 List of Figures 3
  • AMD 3200 | Revision History - Page 4
    2. CPUID Values for AMD Family 15h Models 00h-0Fh G34r1 Processor Revisions 9 Table 3. CPUID Values for AMD Family 15h Models 00h-0Fh C32r1 Processor Revisions 9 Table 4. CPUID Values for AMD Family 15h Models 00h-0Fh AM3r2 Processor Revisions 10 Table 5. Supported Mixed Revision Configurations
  • AMD 3200 | Revision History - Page 5
    October 2012 Revision History Revision Guide for AMD Family 15h Models 00h-0Fh Processors Date October 2012 August 2012 May 2012 November 2011 October 2011 Revision 3.18 3.16 3.12 3.04 3.00 Description Added AMD Opteron™ 3300 Series, 4300 Series, 6300 Series Processors and OR-C0 silicon revision
  • AMD 3200 | Revision History - Page 6
    following products: • AMD FX™-Series Processor • AMD Opteron™ 3200 Series Processor • AMD Opteron™ 3300 Series Processor • AMD Opteron™ 4200 Series Processor • AMD Opteron™ 4300 Series Processor • AMD Opteron™ 6200 Series Processor • AMD Opteron™ 6300 Series Processor This guide consists of these
  • AMD 3200 | Revision History - Page 7
    in the BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors, order# 42301. Each mnemonic is instructions. • PMCxXXX[Y]: performance monitor events; XXX is the hexadecimal event counter number programmed into MSRC001_020[A,8,6,4,2,0][EventSelect] (PERF_CTL[5:0] bits
  • AMD 3200 | Revision History - Page 8
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 • NBPMCxXXX[Y]: northbridge performance monitor events; XXX is the hexadecimal event counter number programmed into MSRC001_024[6,4,2,0][EventSelect] (NB_PERF_CTL[3:0] bits 7:0). Y, when specified, signifies
  • AMD 3200 | Revision History - Page 9
    the revision has not been used in the processor segment. Table 2. CPUID Values for AMD Family 15h Models 00h-0Fh G34r1 Processor Revisions CPUID Fn0000_0001_EAX, D18F4x164[1:0] (Mnemonic) AMD Opteron™ 6200 Series Processor AMD Opteron™ 6300 Series Processor 00600F12h, 1b (OR-B2) 00600F20h, 11b (OR
  • AMD 3200 | Revision History - Page 10
    AMD Family 15h Models 00h-0Fh AM3r2 Processor Revisions CPUID Fn0000_0001_EAX, D18F4x164[1:0] AMD FX™ Series Processor AMD Opteron™ 3200 Series Processor AMD Opteron™ 3300 Series Processor may be specific to some steppings of the processor, and the specified bit may or may not be set on other
  • AMD 3200 | Revision History - Page 11
    . 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors Mixed Processor Revision Support AMD Family 15h processors with different revisions may be mixed in a multiprocessor system. Mixed revision support includes the AMD Opteron™ processor configurations as shown in Table
  • AMD 3200 | Revision History - Page 12
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 4. Read {D18F5x198_x5, D18F5x198_x4} and write this value to MSRC001_0032. 5. value to MSRC001_0034. 7. Read {D18F5x198_xB, D18F5x198_xA} and write this value to MSRC001_0035. 12 Processor Identification
  • AMD 3200 | Revision History - Page 13
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors Operating System Visible Workarounds This section describes how to identify operating system visible workarounds. MSRC001_0140 OS Visible Work-around MSR0 (OSVW_ID_Length) This register, as defined in AMD64 Architecture Programmer's Manual
  • AMD 3200 | Revision History - Page 14
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 Product Errata This section documents product errata for the processors. May Not Indicate Fused Branch 536 Performance Counter for Instruction Cache Misses Does Not Increment for Sequential Prefetches 537
  • AMD 3200 | Revision History - Page 15
    Limit May Cause #GP Exception 637 Processor Does Not Report the Correct DRAM Address for MCA Errors Within the CC6 Save Area 657 MC1_STATUS Enable Bit Not Set When Logging Corrected Errors 658 CPUID Incorrectly Reports Large Page Support in L2 Instruction TLB 659 VMCB Interrupt Shadow Status May
  • AMD 3200 | Revision History - Page 16
    Address for Loads that Cross Address Boundaries 727 Processor Core May Hang During CC6 Resume 734 Processor May Incorrectly Store VMCB Data 737 Processor Does Not Check 128-bit Canonical Address Boundary Case on Logical Address 739 Processor May Read Branch Status Register With Inconsistent Parity
  • AMD 3200 | Revision History - Page 17
    3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors Table 7. Cross-Reference of Processor Revision to Errata (continued) CPUID Fn0000_0001_EAX, D18F4x164[1:0] No. Errata Description 00600F12h 01b (OR-B2) 00600F20h 11b (OR-C0) 745 Processor May Incorrectly Report Cache
  • AMD 3200 | Revision History - Page 18
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 Cross-Reference of Errata to Package Type This table cross-references the errata to each package type. "X" signifies that the
  • AMD 3200 | Revision History - Page 19
    X X 717 X X X 718 X X X 719 X X X 720 X X X 724 X X X 725 X X X 726 X X X 727 X X X 734 X X X 737 X X X 739 X X X 740 X X X 742 X X X 744 X X 745 X Revision Guide for AMD Family 15h Models 00h-0Fh Processors Cross-Reference of Errata to Package Type 19
  • AMD 3200 | Revision History - Page 20
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors Table 8. Cross-Reference of Errata to Package Type (continued) Package Errata AM3r2 C32r1 G34r1 759 X X X 48063 Rev. 3.18 October 2012 20 Cross-Reference of Errata to Package Type
  • AMD 3200 | Revision History - Page 21
    -Reference of Errata to Processor Segments Processor Segment Errata AMD FX ™ -Series Processor AMD Opteron ™ 3200 Processor AMD Opteron ™ 3300 Processor AMD Opteron ™ 4200 Processor AMD Opteron ™ 4300 Processor AMD Opteron ™ 6200 Processor AMD Opteron ™ 6300 Processor 361 X X X X X X X 503
  • AMD 3200 | Revision History - Page 22
    Guide for AMD Family 15h Models 00h-0Fh Processors Table 9. Cross-Reference of Errata to Processor Segments (continued) Processor Segment 48063 Rev. 3.18 October 2012 Errata AMD FX ™ -Series Processor AMD Opteron ™ 3200 Processor AMD Opteron ™ 3300 Processor AMD Opteron ™ 4200 Processor AMD
  • AMD 3200 | Revision History - Page 23
    ) Processor Segment Revision Guide for AMD Family 15h Models 00h-0Fh Processors Errata AMD FX ™ -Series Processor AMD Opteron ™ 3200 Processor AMD Opteron ™ 3300 Processor AMD Opteron ™ 4200 Processor AMD Opteron ™ 4300 Processor AMD Opteron ™ 6200 Processor AMD Opteron ™ 6300 Processor 726
  • AMD 3200 | Revision History - Page 24
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 361 Breakpoint Due to an Instruction That Has an Interrupt Shadow May Be Lost Description A #DB exception occurring in guest mode may be discarded under the following conditions: • A trap-type #DB
  • AMD 3200 | Revision History - Page 25
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 503 APIC Task-Priority Register May Be Incorrect Description An APIC task priority register (TPR) write may use an incorrect internal buffer for the data.
  • AMD 3200 | Revision History - Page 26
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 504 Corrected L3 Errors May Lead to System Hang Description Under a highly specific and detailed set of internal timing conditions that involves corrected L3 errors, a processor read from the L3 cache may
  • AMD 3200 | Revision History - Page 27
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 505 Scrub Rate Control Register Address Depends on DctCfgSel Description When DCT Configuration Select[DctCfgSel] (D18F1x10C[0]) is 1b, accesses to the Scrub Rate Control register (
  • AMD 3200 | Revision History - Page 28
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 520 Some Lightweight Profiling Counters Stop Counting When Instruction-Based Sampling is Enabled Description When Lightweight Profiling (LWP) and Instruction-Based Sampling (IBS) measurement of instruction
  • AMD 3200 | Revision History - Page 29
    2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 535 Lightweight Profiling May Not Indicate Fused Branch Description The Lightweight Profiling (LWP) fused operation bit (FUS - bit 28 of the branch retired event record, LWP EventId 3) may not be set when the processor core is
  • AMD 3200 | Revision History - Page 30
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 536 Performance Counter for Instruction Cache Misses Does Not Increment for Sequential Prefetches Description PMCx081 (Instruction Cache Misses) does not increment for L1 instruction cache misses that are due
  • AMD 3200 | Revision History - Page 31
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 537 Performance Counter for Ineffective Software Prefetches Does Not Count for L2 Hits Description PMCx052[3] (ineffective software prefetch due to an L2 cache hit) does
  • AMD 3200 | Revision History - Page 32
    Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 538 Performance Counter Does Not Count for Some Retired Micro-Ops Description Some instructions with F0h in the opcode byte are incorrectly detected by the processor core as empty microops, causing the processor core
  • AMD 3200 | Revision History - Page 33
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 540 GART Table Walk Probes May Cause System Hang Description Probes that are generated for GART table walks may overflow internal queues and lead to a
  • AMD 3200 | Revision History - Page 34
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 550 Latency Performance Counters Are Not Accurate Description Latency performance counters NBPMCx1E2 through NBPMCx1E7 are not accurate when L3 speculative
  • AMD 3200 | Revision History - Page 35
    byte lane) and all populated DIMMs = 111b, BIOS should set DataTxFifoWrDly (D18F2x210_dct[1:0]_nbp[3:0] bits 18:16) as specified in the BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors, order# 42301, but with a minimum value of 010b. Fix Planned No fix planned
  • AMD 3200 | Revision History - Page 36
    for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 586 A Far Control Transfer Changing Processor Operating Mode May Generate a False Machine Check Description A far control transfer that changes the processor operating mode may erroneously indicate a decoder instruction
  • AMD 3200 | Revision History - Page 37
    2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 592 VPEXTRQ and VPINSRQ May Not Signal Invalid-Opcode Exception Description Advanced Vector Extensions (AVX) variants of legacy SSE instructions normally promote the size of a GPR operand using VEX.W. When running in 32-bit legacy
  • AMD 3200 | Revision History - Page 38
    Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 593 Last-Branch Record Enabled May Cause Machine Check and Incorrect LastBranchToIp Description When LBR is enabled, a complex interaction between two threads of the same compute-unit may result in the processor core
  • AMD 3200 | Revision History - Page 39
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 600 HyperTransport™ Link Retry Due to Partial CRC Error May Cause System Hang Description The northbridge may stall when a probe hit returning data occurs simultaneously
  • AMD 3200 | Revision History - Page 40
    DllProcessFreqCtlOverride, DllProcessFreqCtlIndex2] settings (D18F4x1[9C,94,8C,84]_x[5:4][9:0][8,0]F_dm[1] bits 12 and 3:0). These settings are specific to each Gen3 frequency in the BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors, order# 42301. Fix Planned No
  • AMD 3200 | Revision History - Page 41
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 608 P-state Limit Changes May Not state limit changes, resulting in either one of the following conditions: • The processor runs continuously in a lower performance (higher numbered) P-state than is actually
  • AMD 3200 | Revision History - Page 42
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 619 Non-Posted Reads May Block Write Dependent on Probe Responses Description The northbridge may stall indefinitely on non-posted
  • AMD 3200 | Revision History - Page 43
    Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 623 Small Code Segment Limits May Cause Incorrect Limit Faults Description In cases where the code segment limit is less than 0_0020h and the Granularity (G) bit is zero, the processor reports an incorrect #GP
  • AMD 3200 | Revision History - Page 44
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 624 SB-RMI Processor State Accesses May Persistently Timeout if Interrupted by a Warm Reset Description The assertion of a warm reset during a small timing window of an APML SB-RMI processor state access may
  • AMD 3200 | Revision History - Page 45
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 625 SB-RMI Writes May Not Be Observed by Processor Description After a write using the APML SB-RMI interface to either the Inbound Message Registers (SBRMI_x3[F:8]) or Software Interrupt Register (SBRMI_x40),
  • AMD 3200 | Revision History - Page 46
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 636 Instruction Addresses Near Canonical Address Limit May Cause #GP Exception Description The processor may incorrectly generate a #GP exception when an instruction executes within a small window of the
  • AMD 3200 | Revision History - Page 47
    Guide for AMD Family 15h Models 00h-0Fh Processors 637 Processor Does Not Report the Correct DRAM Address for MCA Errors Within the CC6 Save Area Description While reporting an ECC machine check error in the core C6 (CC6) save area, the processor CPUID Fn8000_001e_ECX[NodeId, bits 7:0]), but in
  • AMD 3200 | Revision History - Page 48
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 containing the [23:21]
  • AMD 3200 | Revision History - Page 49
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 657 MC1_STATUS Enable Bit Not Set When Logging Corrected Errors Description The processor does not set MC1_STATUS[En] = 1b (MSR0000_0405[60]) when logging an enabled and corrected error in the IF machine
  • AMD 3200 | Revision History - Page 50
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 658 CPUID Incorrectly Reports Large Page Support in L2 Instruction TLB Description The CPUID instruction incorrectly reports the number of entries and the associativity of 2 MB, 4 MB and 1 GB TLB entries in
  • AMD 3200 | Revision History - Page 51
    Guide for AMD Family 15h Models 00h-0Fh Processors 659 VMCB Interrupt Shadow Status May Be Incorrect Description The processor may fail to clear the VMCB INTERRUPT_SHADOW field (VMCB offset 068h bit 0) when intercepting or interrupting an SVM guest that is executing a Move String instruction
  • AMD 3200 | Revision History - Page 52
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 660 APERF May Increase Unpredictably 48063 Rev. 3.18 October 2012 Description The value of MSR0000_00E8 (APERF) may increase unpredictably after any of the following events: • A P-state transition, including those performed due to core
  • AMD 3200 | Revision History - Page 53
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 661 P-State Limit and Stop Clock Assertion May Cause System Hang Description A P-state limit change that occurs within a small timing window of a Stop Clock assertion may result in DRAM not entering self-
  • AMD 3200 | Revision History - Page 54
    Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 663 Local Interrupts LINT0/LINT1 May Occur While APIC is Software Disabled Description The processor Control Register[LintEn] (D18F0x68[16]) = 1b. If this bit is set while the APIC is software disabled, an ExtInt or
  • AMD 3200 | Revision History - Page 55
    Guide for AMD Family 15h Models 00h-0Fh Processors 667 Processor May Generate Incorrect P-state Limit Interrupts Description P-state limit changes due to SB-RMI (SBI P-state Limit[PstateLimit], MSRC001_0072[10 bits [PslApicLoEn, PslApicHiEn] are not both zero (D18F3x64[7:6] != 00b). The processor
  • AMD 3200 | Revision History - Page 56
    Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 668 Load Operation May Receive Incorrect Data After Floatingpoint Exception Description The processor bit 5) and a prior exception is indicated (x87 Status Word Register Exception Status, FSW.ES bit processor core. AMD
  • AMD 3200 | Revision History - Page 57
    Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 671 Debug Breakpoint on Misaligned Store first set MSRC001_1000[17] = 1b. AMD recommends this workaround be enabled with AMD Opteron™ processors. For all other processors, BIOS should disable the workaround by
  • AMD 3200 | Revision History - Page 58
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 672 SVM Guest Performance Suggested Workaround Contact your AMD representative for information on a BIOS update. When the workaround is enabled, the processor swaps the HostGuestOnly bits (i.e. bits 41 and 40
  • AMD 3200 | Revision History - Page 59
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 673 Misaligned Page Crossing String Operations May Cause System Hang Description A misaligned Move String or Store String instruction with a REP prefix that crosses a page boundary may cause a system hang.
  • AMD 3200 | Revision History - Page 60
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 674 Processor May Cache Prefetched Data from Remapped Memory Region Description Prefetches from a write back (WB) DRAM memory region may persist when that memory region is remapped
  • AMD 3200 | Revision History - Page 61
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 675 Instructions Performing Read-Modify-Write May Alter Architectural State Before #PF Description An instruction performing a read-modify-write operation may be presented with a page fault (#PF) after
  • AMD 3200 | Revision History - Page 62
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 685 Some Processor Cores May Have Inaccurate Instruction Cache Fetch Performance Counter Description The processor may over-report PMCx080 (instruction cache fetches) when the performance monitor is enabled
  • AMD 3200 | Revision History - Page 63
    Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 689 AM3r2 Six Core Processor May Limit P-State When Core C6 State Is Disabled Description If system software disables core C6 state (CC6) on an AMD FX™ 6100 Six-Core Processor, OPN FD6100WMW6KGU, the application
  • AMD 3200 | Revision History - Page 64
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 overlaps the read pointer of a synchronization FIFO between the processor core and the northbridge. Potential Effect on System Unpredictable system behavior, takes effect. Fix Planned No fix planned 64 Product Errata
  • AMD 3200 | Revision History - Page 65
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 691 Processors Using 1 MB L3 Subcaches May Execute a WriteBack Invalidate Operation Incorrectly Description The processor may fail to flush the full address range of L3 cache when executing a WBINVD instruction, or INVD instruction with
  • AMD 3200 | Revision History - Page 66
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 693 Performance Counter May Incorrectly Count MXCSR Loads Description The processor may incorrectly increment the following performance counter due to XRSTOR, FXRSTOR, LDMXCSR or VLDMXCSR instructions loading
  • AMD 3200 | Revision History - Page 67
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 694 IBS Sampling of Instruction Fetches May Be Uneven Description Instructions selected for instruction-based sampling (IBS) of fetch performance (Fetch Control[IbsFetchEn], MSRC001_1030[48] = 1b) may be
  • AMD 3200 | Revision History - Page 68
    executes with invalid operands while invalid operations are unmasked (FCW.IM, bit 0 = 0b). • The processor may set the FERR signal incorrectly after an FLDCW instruction updates the floating-point control word mask bits (FCW[5:0]). A subsequent floating point operation may then result in an
  • AMD 3200 | Revision History - Page 69
    Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 699 Processor May Generate Illegal Access in VMLOAD or VMSAVE Instruction Description The processor may generate a speculative access during execution of a VMLOAD or VMSAVE instruction. The memory type used for
  • AMD 3200 | Revision History - Page 70
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 704 Processor May Report Incorrect Instruction Pointer Description Under a highly specific and detailed set of internal timing conditions, the processor may store an incorrect instruction pointer (rIP) while
  • AMD 3200 | Revision History - Page 71
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 707 Performance Counter for Locked Operations May Count Cycles from Non-Locked Operations Description PMCx024[2] may include cycles spent performing non-locked operations. Potential Effect
  • AMD 3200 | Revision History - Page 72
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 708 Initial Value of Time Stamp Counter May Include an Offset Error Description During the interval of time between the northbridge observing the RESET# deassertion and the processor cores initializing
  • AMD 3200 | Revision History - Page 73
    3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 709 Processor May Be Limited to Minimum P-state After a Pstate Limit Change Description Following a change to the P-state limit or a core C6 (CC6) exit, the processor may incorrectly restrict the processor to the lowest
  • AMD 3200 | Revision History - Page 74
    is equal to BA000020_000B0C0F. Bit 62 (error overflow) or bit 59 (miscellaneous valid) of MC4_STAT may or may not be set. • Bits 5:1 of the MC4_ADDR core and northbridge frequencies. AMD has only observed this erratum with one G34 processor configuration where the software P-state 0 core frequency
  • AMD 3200 | Revision History - Page 75
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 717 Instruction-Based Sampling May Be Inaccurate Description The processor may experience sampling inaccuracies when Instruction-Based Sampling (IBS) is enabled in the following cases: • When IBS Op Data 3
  • AMD 3200 | Revision History - Page 76
    Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 718 Instruction-Based Sampling May Be Inaccurate Description The processor may experience sampling inaccuracies when Instruction-Based Sampling (IBS) is enabled in the following cases: • The processor These bits would
  • AMD 3200 | Revision History - Page 77
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 719 Instruction-Based Sampling Fetch Counter Always Starts at Maximum Value Description When setting IBS Fetch Control Register[IbsFetchEn] = 1b to enable IBS fetch sampling, the periodic
  • AMD 3200 | Revision History - Page 78
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 720 Processor May Not Respect Interrupt Shadow Description Under a highly specific and detailed set of internal timing conditions, a #DB exception may be presented during execution of an instruction that is
  • AMD 3200 | Revision History - Page 79
    not observe a write that is performed by another processor core. AMD has not observed this effect in any commercially available software. Suggested Workaround Hypervisors should intercept HLT instructions by setting VMCB.Intercept_HLT (offset 00Ch bit 24) to 1b. Fix Planned No fix planned Product
  • AMD 3200 | Revision History - Page 80
    Guide for AMD Family 15h Models 00h-0Fh Processors 725 Incorrect APIC Remote Read Behavior 48063 Rev. 3.18 October 2012 Description The processor performed using Interrupt Command Register Low[MsgType] of 011b (APIC300[10:8]). The processor may, but does not always, provide an error indication in
  • AMD 3200 | Revision History - Page 81
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 726 Processor May Report Incorrect MCA Address for Loads that Cross Address Boundaries Description In the event that a line fill error or system read data error is reported for some, but not all, bytes of an unaligned load instruction
  • AMD 3200 | Revision History - Page 82
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 727 Processor Core May Hang During CC6 Resume Description During a resume from core C6 (CC6) state, the processor may hang. Potential Effect on System Processor core hang, usually resulting in a system hang.
  • AMD 3200 | Revision History - Page 83
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 734 Processor May Incorrectly Store VMCB Data Description Under a highly specific and detailed set of internal timing conditions during a #VMEXIT for a virtual machine guest that has multiple
  • AMD 3200 | Revision History - Page 84
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 737 Processor Does Not Check 128-bit Canonical Address Boundary Case on Logical Address Description The processor core may not detect a #GP exception if the processor is in 64-bit mode and the logical address
  • AMD 3200 | Revision History - Page 85
    48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 739 Processor May Read Branch Status Register With Inconsistent Parity Bit Description Under a highly specific and detailed set of internal timing conditions, the processor may read an internal branch status
  • AMD 3200 | Revision History - Page 86
    Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 740 Lightweight Profiling May Cause System Hang with Concurrent Stop Clock Description The processor record to be stored. Only LWP record type 2 (instructions retired) or LWP record type 3 (branches retired) events
  • AMD 3200 | Revision History - Page 87
    DIMMs support ECC. Potential Effect on System All future reads of the memory attached to the affected DRAM controller return unpredictable data. The processor may recommended by the BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors, order# 42301 section "DRAM Phy
  • AMD 3200 | Revision History - Page 88
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 744 Processor CC6 May Not Restore Trap Registers Description Following a core C6 (CC6) power state transition, the processor core may not restore the following registers: • MSRC001_0053, IO Trap Register 3 •
  • AMD 3200 | Revision History - Page 89
    being shared between two processor cores. On the above-mentioned processor models, the instruction cache and the L2 cache are not shared and software would not find two processor cores that reported the same Compute Unit ID (CPUID Fn8000_001E_EBX[ComputeUnitID, bits 7:0]). Potential Effect on System
  • AMD 3200 | Revision History - Page 90
    Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 759 One Core May Observe a Time Stamp Counter Skew Description During a P-state change or following a C-state change, the processor core may synchronize an internal copy of the time stamp counter (TSC)
  • AMD 3200 | Revision History - Page 91
    -0Fh Processors Documentation Support The following documents provide additional information regarding the operation of the processor: • BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors, order# 42301 • AMD64 Architecture Programmer's Manual Volume 1: Application
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Revision
Guide
for
AMD
Family
15
h
Models
00
h-
0
Fh
Processors
Publication #
48063
Revision:
3.18
Issue Date:
October 2012
Advanced
Micro
Devices