AMD 3200 Revision History - Page 35
Incorrect, Memory, Controller, Operation, WrDatGrossDly, Setting, MEMCLKs - + 64
UPC - 730143241144
View all AMD 3200 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 35 highlights
48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 585 Incorrect Memory Controller Operation Due to a WrDatGrossDly Setting of 3.5 MEMCLKs Description The memory controller may incorrectly issue a ZQ command during a 64-byte write operation when WrDatGrossDly is set to a value of 3.5 MEMCLKs (111b). Potential Effect on System Undefined system behavior. Suggested Workaround If WrDatGrossDly (D18F2x9C_x0000_0[3:0]0[3:1]_dct[1:0]) for all byte lanes (including the ECC byte lane) and all populated DIMMs = 111b, BIOS should set DataTxFifoWrDly (D18F2x210_dct[1:0]_nbp[3:0] bits 18:16) as specified in the BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors, order# 42301, but with a minimum value of 010b. Fix Planned No fix planned Product Errata 35