AMD 3200 Revision History - Page 27
Scrub, Control, Register, Address, Depends, DctCfgSel
UPC - 730143241144
View all AMD 3200 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 27 highlights
48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 505 Scrub Rate Control Register Address Depends on DctCfgSel Description When DCT Configuration Select[DctCfgSel] (D18F1x10C[0]) is 1b, accesses to the Scrub Rate Control register (D18F3x58) incorrectly accesses a different register that does not actually affect any hardware. Potential Effect on System Incorrect scrub rate controls may be read or in effect. Suggested Workaround Software should clear DctCfgSel (D18F1x10C[0]) to 0b prior to any access to D18F3x58 Scrub Rate Control Register. The software must serialize any accesses to D18F3x58 with other accesses to registers that use DctCfgSel. When enabling scrub settings, BIOS should write D18F3x58 twice with the same value - once with D18F1x10C[0] set to 0b and once with D18F1x10C[0] set to 1b. BIOS should program D18F1x10C[0] to 0b before handing over control to the operating system. Fix Planned No fix planned Product Errata 27