AMD 3200 Revision History - Page 37
VPEXTRQ, VPINSRQ, Signal, Invalid-Opcode, Exception
UPC - 730143241144
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48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 592 VPEXTRQ and VPINSRQ May Not Signal Invalid-Opcode Exception Description Advanced Vector Extensions (AVX) variants of legacy SSE instructions normally promote the size of a GPR operand using VEX.W. When running in 32-bit legacy or compatibility modes, setting VEX.W=1 is nonsensical and VEX.W is ignored. VPEXTRQ and VPINSRQ are an exception to that general rule and are specified to generate a Invalid-Opcode (#UD) exception. In violation of this, the processor does not signal #UD exception for AVX instructions VPEXTRQ and VPINSRQ when VEX.W=1 and the processor is running in 32-bit legacy or compatibility modes. Instead, the instruction is executed as if VEX.W=0. Potential Effect on System None expected. These opcode encodings are not expected to be generated by software. Suggested Workaround Software should only generate VPEXTRQ and VPINSRQ instructions with VEX.W=0 when operating in 32-bit modes and not depend on generating a #UD with VEX.W=1. Fix Planned Yes Product Errata 37