AMD 3200 Revision History - Page 54
Local, Interrupts, Occur, While, Software, Disabled
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Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 663 Local Interrupts LINT0/LINT1 May Occur While APIC is Software Disabled Description The processor unmasks local interrupts (LINT0 and LINT1) while the APIC is software disabled (SpuriousInterrupt Vector Register[APICSWEn], APICF0[8] = 0b). The LINT[1:0] LVT entry mask bits (APIC3[60:50] bit 16) are cleared and cannot be set. Broadcast ExtInt and NMI interrupt requests can be converted to LINT0 and LINT1 local interrupts respectively by setting Link Transaction Control Register[LintEn] (D18F0x68[16]) = 1b. If this bit is set while the APIC is software disabled, an ExtInt or NMI interrupt causes an unexpected local interrupt. Potential Effect on System Software may receive a local interrupt that was not expected, possibly leading to a system crash. Suggested Workaround BIOS should set MSRC001_001F[23] = 1b before enabling the APIC (APIC_BAR[ApicEn] (MSR0000_001B[11]) = 1b) or before setting Link Transaction Control[LintEn] (D18F0x68[16]) = 1b. Fix Planned No fix planned 54 Product Errata