AMD 3200 Revision History - Page 60
Processor, Cache, Prefetched, Remapped, Memory, Region
UPC - 730143241144
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Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 674 Processor May Cache Prefetched Data from Remapped Memory Region Description Prefetches from a write back (WB) DRAM memory region may persist when that memory region is remapped to an uncacheable (UC) or write combining (WC) memory type. Potential Effect on System Data could be cached in a modified state from the remapped memory region, which will not be probed, however this can only occur if a prefetch operation persists through the invalidation or flushing of TLB entries and cache lines before the remapped memory region is accessible in a coherent manner. There have been no observations of this erratum on silicon. Suggested Workaround None recommended. Optionally, system software may set MSRC001_1022[13] = 1b (DC_CFG[DisHwPf]) during system boot if frequent run-time remapping of memory types as described is expected. Fix Planned Yes 60 Product Errata