AMD 3200 Revision History - Page 75
Instruction-Based, Sampling, Inaccurate
UPC - 730143241144
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48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 717 Instruction-Based Sampling May Be Inaccurate Description The processor may experience sampling inaccuracies when Instruction-Based Sampling (IBS) is enabled in the following cases: • When IBS Op Data 3 Register[IbsDcMiss] (MSRC001_1037[7]) is 0b, IBS Op Data 3 Register[IbsDcMabHit] (MSRC001_1037[16])] should always be 0b. However, the processor may incorrectly set IbsDcMabHit. • When the processor samples an instruction that is altering the CS_BASE value, the IbsOpRip reported in IBS Op Logical Address (MSRC001_1034) may be determined using an incorrect CS_BASE. • In rare instances, a tagged branch may set an inaccurate value in IBS Branch Target Address Register (MSRC001_103B). Potential Effect on System Inaccuracies in performance monitoring software may be experienced. Suggested Workaround The following workarounds can be used for the above issues: • Performance monitoring software should treat IBS Op Data 3 Register[IbsDcMabHit] (MSRC001_1037[16]) as 0b when MSRC001_1037[7] is 0b. • No workaround is necessary for IbsOpRip when CS_BASE is zero. CS_BASE is normally zero in commercially available software. • Performance monitoring software should not rely on the value in MSRC001_103B (IbsBrTarget). Fix Planned Yes Product Errata 75