AMD AXDA3200DKV4E Data Sheet - Page 38

Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet 26237C-May 2003 7.2 Advanced 400 FSB AMD Athlon™ XP Processor Model 10 SYSCLK and SYSCLK# AC Characteristics Table 6. Table 6 shows the SYSCLK/SYSCLK# differential clock AC characteristics of this processor. Advanced 400 FSB SYSCLK and SYSCLK# AC Characteristics Symbol Parameter Description Minimum Maximum Units Notes Clock Frequency 50 200 MHz 1 Duty Cycle 30% 70% t1 Period t2 High Time t3 Low Time t4 Fall Time t5 Rise Time Period Stability 5 ns 2, 3 1.0 ns 1.0 ns 1.5 ns 1.5 ns ± 300 ps Notes: 1. The AMD Athlon™ system bus operates at twice this clock frequency. 2. Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL to track the jitter. The -20dB attenuation point, as measured into a 20- or 30-pF load must be less than 500 kHz. 3. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above. AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a maximum rate of 100 kHz. Figure 9 shows a sample waveform of the SYSCLK signal. t2 VCROSS VThreshold-AC t3 t5 Figure 9. SYSCLK Waveform t4 t1 26 Advanced 400 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications Chapter 7