AMD AXDA3200DKV4E Data Sheet - Page 41

Electrical Data, 8.1 Conventions, 8.2 Interface Signal Groupings

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26237C-May 2003 Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet 8 Electrical Data This chapter describes the electrical characteristics that apply to all desktop AMD Athlon™ XP processors model 10. 8.1 Conventions The conventions used in this chapter are as follows: ■ Current specified as being sourced by the processor is negative. ■ Current specified as being sunk by the processor is positive. 8.2 Interface Signal Groupings The electrical data in this chapter is presented separately for each signal group. Table 9 defines each group and the signals contained in each group. Table 9. Interface Signal Groupings Signal Group Signals Power VID[4:0], VCCA, VCC_CORE, COREFB, COREFB# Frequency FID[3:0] SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN# System Clocks and RSTCLK/RSTCLK#), PLLBYPASSCLK#, PLLBYPASSCLK Notes See "Voltage Identification (VID[4:0])" on page 30, "VID[4:0] Pins" on page 77, "VCCA AC and DC Characteristics" on page 31, "VCC_CORE Characteristics" on page 32, "VCCA Pin" on page 77, and "COREFB and COREFB# Pins" on page 73. See "Frequency Identification (FID[3:0])" on page 31 and "FID[3:0] Pins" on page 74. See Table 15, "SYSCLK and SYSCLK# DC Characteristics," on page 35, Table 2, "Advanced 333 FSB SYSCLK and SYSCLK# AC Characteristics," on page 22, Table 6, "Advanced 400 FSB SYSCLK and SYSCLK# AC Characteristics," on page 26, "SYSCLK and SYSCLK#" on page 77, and "PLL Bypass and Test Pins" on page 76. Chapter 8 Electrical Data 29

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Chapter 8
Electrical Data
29
26237C—May 2003
AMD Athlon™ XP Processor Model 10 Data Sheet
Preliminary Information
8
Electrical Data
This chapter describes the electrical characteristics that apply
to all desktop AMD Athlon™ XP processors model 10.
8.1
Conventions
The conventions used in this chapter are as follows:
■
Current specified as being sourced by the processor is
negative
.
■
Current specified as being sunk by the processor is
positive
.
8.2
Interface Signal Groupings
The electrical data in this chapter is presented separately for
each signal group.
Table 9 defines each group and the signals contained in each
group.
Table 9.
Interface Signal Groupings
Signal Group
Signals
Notes
Power
VID[4:0], VCCA, V
CC_CORE
, COREFB,
COREFB#
See “Voltage Identification (VID[4:0])” on page 30,
“VID[4:0] Pins” on page 77, “VCCA AC and DC
Characteristics” on page 31, “V
CC_CORE
Characteristics”
on page 32, “VCCA Pin” on page 77, and “COREFB and
COREFB# Pins” on page 73.
Frequency
FID[3:0]
See “Frequency Identification (FID[3:0])” on page 31 and
“FID[3:0] Pins” on page 74.
System Clocks
SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN#
and RSTCLK/RSTCLK#), PLLBYPASSCLK#,
PLLBYPASSCLK
See Table 15, “SYSCLK and SYSCLK# DC Characteristics,”
on page 35, Table 2, “Advanced 333 FSB SYSCLK and
SYSCLK# AC Characteristics,” on page 22, Table 6,
“Advanced 400 FSB SYSCLK and SYSCLK# AC
Characteristics,” on page 26, “SYSCLK and SYSCLK#” on
page 77, and “PLL Bypass and Test Pins” on page 76.