Foxconn A7GM-S English Manual. - Page 37

Advanced Chipset Features CMOS Setup Utility - Copyright (C) 1985-2006, American Megatrends, Inc. Advanced Chipset Features Northbridge Chipset Configuration Help Item ► Memory Configuration [Press Enter] ► DRAM Timing Configuration [Press Enter] CAS Latency :4 CLK RAS/CAS Delay :4 CLK Row Precharge Time :4 CLK Min Active RAS :12 CLK RAS/RAS Delay :2 CLK Row Cycle :17 CLK Internal Graphics Configuration Internal Graphics Mode UMA Frame Buffer Size GFX Engine Clock Surround View VBIOS Type NB Azalia [Enabled] [Auto] [500] [Disabled] [HDMI] [Enabled] Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help F9:Optimized Defaults ► Memory Configuration / DRAM Timing Configuration Press to go to its submenu. 3 The following six items display the values configured at the settings of "DRAM Timing Mode". ► CAS Latency This item shows the CAS latency. The CAS Latency is the number of clock cycles that elapse from the time the request for data is sent to the actual memory location until the data is transmitted from the module. ► RAS / CAS Delay This item displays a delay time (in clock cycles) between the CAS and RAS strobe signals. ► Row Precharge Time This item shows the number of clock cycles taken between issuing of the precharge command and the active command. The DRAM row precharge time is in unit of clock cycle. ► Min Active RAS Displays the number of clock cycles taken between a bank active command and issuing of the precharge command. ► RAS / RAS Delay This item shows a delay time (in clock cycles) between the RAS and RAS strobe signals. ► Row Cycle This item displays the minimum timing interval between successive active commands to the same bank. The row cycle time is in unit of clock cycle. ► Internal Graphics Mode Enable/Disable the integrated UMA graphics controller, ► UMA Frame Buffer Size Allocates system memory for use as video memory to ensure the most efficient use of available resources for maximum 2D/3D graphics performance. This is a memory allocation method addition to the Unified Memory Architecture (UMA) 30