HP Integrity Superdome SX1000 Site Preparation Guide, Fifth Edition - HP Integ - Page 102

Configuration Guidelines Configuration Guidelines Configuration Guidelines To achieve the best performance and high availability consider the following factors as shown in order of importance: 1. Memory Population 2. Cell Population 3. Partition Size 4. I/O Chassis Allocation Memory Population Each cell has two memory busses that must be evenly populated to achieve full bandwidth and reduce latency. Configurations of 4 Gbytes, 8 Gbytes, 12 Gbytes, 16 Gbytes, and 32 GBytes per cell accomplish this. Memory must be symmetric within each partition for interleaving to be even across all the cells, otherwise performance problems can result. Consider the following example: Example B-1 Incorrect Memory Distribution Across Partitions If a two cell partition has 2 Gbytes of memory on one cell and 16 Gbytes on another, 4 Gbytes will be interleaved (two from each cell) and 14 Gbytes will be assigned to one cell only. This will result in inconsistent bandwidth and latency problems. Cell Population A group of four cells (a quad) resides on one Crossbar Chip (XBC) and has the lowest latency. Quads are slots 0-3, 4-7, 8-11 and 12-15. Keep partitions with a size less than or equal to four on the same quad. Memory traffic from one quad to another is routed in pairs. The following pairs share the same path: 0 and 1, 2 and 3, 4 and 5, and 6 and 7. The hp Integrity Superdome SD32 or hp 9000 Superdome SD32 can have dual links between quads if U-turns are installed on the backplane. To use both links a six-cell partition uses slots 0-3, 5, and 7 as would 4 and 6. Partitions that share links share common points of failure. XBC-XBC links can saturate and kill performance. An eight-cell partition on an SD6400 should be spread across cabinets. Cab 0, slots 0-3, 5, 7 and Cab 1, slots 4 and 6. Partition Size For best performance, partitions should be either single cell or greater powers of 2: 2, 4, 8, and 16 cells. Memory interleaving is performed by taking either four or six physical address bits and using them to index into a cell mapping table entry consisting of 16 or 64 sub-entries. For a single cell partition, each sub-entry is loaded with only one cell. A two-cell partition alternates between the two cells. There is one 64 sub-entry cell map entry and a 48-16 sub-entry cell entry. Partitions that are not powers of two will undergo revisiting. Consecutive accesses will go through all the cell boards and come back through revisiting as many cells as necessary until all memory is utilized and the 64-entry table is filled. 94 Appendix B