Intel BLKDH61WWB3 Product Specification - Page 67

Port 80h POST Codes

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Error Messages and Beep Codes 4.5 Port 80h POST Codes During the POST, the BIOS generates diagnostic progress codes (POST codes) to I/O port 80h. If the POST fails, execution stops and the last POST code generated is left at port 80h. This code is useful for determining the point where an error occurred. Displaying the POST codes requires a POST card that can interface with the Low Pin Count (LPC) Debug header. The POST card can decode the port and display the contents on a medium such as a seven-segment display. Refer to the location of the LPC Debug header in Figure 1. The following tables provide information about the POST codes generated by the BIOS: • Table 37 lists the Port 80h POST code ranges • Table 38 lists the Port 80h POST codes themselves • Table 39 lists the Port 80h POST sequence NOTE In the tables listed above, all POST codes and range values are listed in hexadecimal. Table 37. Port 80h POST Code Ranges Range 0x00 - 0x05 0x10, 0x20, 0x30, 0x40, 0x50 0x08 - 0x0F 0x11 - 0x1F 0x21 - 0x29 0x2A - 0x2F 0x31 - 0x35 0x36 - 0x3F 0x41 - 0x4F 0x50 - 0x5F 0x60 - 0x6F 0x70 - 0x7F 0x80 - 0x8F 0x90 - 0x9F 0xA0 - 0xAF 0xB0 - 0xBF 0xC0 - 0xCF 0xD0 - 0xDF 0xF0 - 0xFF Subsystem Entering SX states S0 to S5. Resuming from SX states. 0x10 -0x20 - S2, 0x30 - S3, etc. Security (SEC) phase PEI phase pre MRC execution MRC memory detection PEI phase post MRC execution Recovery Platform DXE driver CPU Initialization (PEI, DXE, SMM) I/O buses: PCI, USB, ATA, etc. 0x5F is an unrecoverable error. Start with PCI. BDS Output devices: All output consoles. For future use Input devices: Keyboard/Mouse. For future use Boot Devices: Includes fixed media and removable media. Not that critical since consoles should be up at this point. For future use For future use 67

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Error Messages and Beep Codes
67
4.5
Port 80h POST Codes
During the POST, the BIOS generates diagnostic progress codes (POST codes) to I/O
port 80h.
If the POST fails, execution stops and the last POST code generated is left
at port 80h.
This code is useful for determining the point where an error occurred.
Displaying the POST codes requires a POST card that can interface with the Low Pin
Count (LPC) Debug header.
The POST card can decode the port and display the
contents on a medium such as a seven-segment display.
Refer to the location of the
LPC Debug header in Figure 1.
The following tables provide information about the POST codes generated by the
BIOS:
•
Table 37 lists the Port 80h POST code ranges
•
Table 38 lists the Port 80h POST codes themselves
•
Table 39 lists the Port 80h POST sequence
NOTE
In the tables listed above, all POST codes and range values are listed in hexadecimal.
Table 37.
Port 80h POST Code Ranges
Range
Subsystem
0x00 – 0x05
Entering SX states S0 to S5.
0x10, 0x20, 0x30, 0x40, 0x50
Resuming from SX states. 0x10 –0x20 – S2, 0x30 – S3, etc.
0x08 – 0x0F
Security (SEC) phase
0x11 – 0x1F
PEI phase pre MRC execution
0x21 – 0x29
MRC memory detection
0x2A – 0x2F
PEI phase post MRC execution
0x31 – 0x35
Recovery
0x36 – 0x3F
Platform DXE driver
0x41 – 0x4F
CPU Initialization (PEI, DXE, SMM)
0x50 – 0x5F
I/O buses:
PCI, USB, ATA, etc. 0x5F is an unrecoverable error. Start
with PCI.
0x60 – 0x6F
BDS
0x70 – 0x7F
Output devices:
All output consoles.
0x80 – 0x8F
For future use
0x90 – 0x9F
Input devices:
Keyboard/Mouse.
0xA0 – 0xAF
For future use
0xB0 – 0xBF
Boot Devices:
Includes fixed media and removable media. Not that
critical since consoles should be up at this point.
0xC0 – 0xCF
For future use
0xD0 – 0xDF
For future use
0xF0 – 0xFF