Intel BLKDH61WWB3 Product Specification - Page 68

Intel Desktop Board DH61WW Technical Product Specification Table 38. Port 80h POST Codes Port 80 Code Progress Code Enumeration 0x00,0x01,0x02,0x03,0x04,0x05 0x10,0x20,0x30,0x40,0x50 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x21 0x23 0x24 0x27 0x28 0x29 0x2A 0x2B ACPI S States Entering S0, S2, S3, S4, or S5 state Resuming from S2, S3, S4, S5 Security Phase (SEC) Starting BIOS execution after CPU BIST SPI prefetching and caching Load BSP microcode Load APs microcodes Platform program baseaddresses Wake Up All APs Initialize NEM Pass entry point of the PEI core PEI before MRC PEI Platform driver Set bootmode, GPIO init Early chipset register programming including graphics init Basic PCH init, discrete device init (1394, SATA) LAN init Exit early platform init driver PEI SMBUS SMBUSriver init Entry to SMBUS execute read/write Exit SMBUS execute read/write PEI CK505 Clock Programming Entry to CK505 programming Exit CK505 programming PEI Over-Clock Programming Entry to entry to PEI over-clock programming Exit PEI over-clock programming Memory MRC entry point Reading SPD from memory DIMMs Detecting presence of memory DIMMs Configuring memory Testing memory Exit MRC driver PEI after MRC Start to Program MTRR Settings Done Programming MTRR Settings continued 68