Intel E6320 Specification Update - Page 12

Errata (Sheet 3 of 5) Number Steppings D-2 Q-0 Status BJ54 X X No Fix BJ55 X X No Fix BJ56 X X No Fix BJ57 X X No Fix BJ58 X X No Fix BJ59 X X No Fix BJ60 X X No Fix BJ61 X X No Fix BJ62 X X No Fix BJ63 X X No Fix BJ64 X X No Fix BJ65 X X No Fix BJ66 X X No Fix BJ67 X X No Fix BJ68 X X No Fix BJ69 X X No Fix BJ70 X X No Fix BJ71 X X No Fix BJ72 X X No Fix BJ73 X X No Fix BJ74 X X No Fix BJ75 X X No Fix BJ76 X X No Fix BJ77 X X No Fix BJ78 X X No Fix BJ79 X X No Fix BJ80 X X No Fix BJ81 X X No Fix BJ82 X X No Fix ERRATA A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain Conditions Instruction Fetch May Cause Machine Check if Page Size and Memory Type Was Changed Without Invalidation Reception of Certain Malformed Transactions May Cause PCIe* Port to Hang Rather Than Reporting an Error PCIe* LTR Incorrectly Reported as Being Supported Performance-Counter Overflow Indication May Cause Undesired Behavior XSAVE Executed During Paging-Structure Modification May Cause Unexpected Processor Behavior C-state Exit Latencies May be Higher Than Expected MSR_Temperature_Target May Have an Incorrect Value in the Temperature Control Offset Field Intel® VT-d Interrupt Remapping Will Not Report a Fault if Interrupt Index Exceeds FFFFH PCIe* Link Speed May Not Change From 5.0 GT/s to 2.5 GT/s L1 Data Cache Errors May be Logged With Level Set to 1 Instead of 0 An Unexpected Page Fault or EPT Violation May Occur After Another Logical Processor Creates a Valid Translation for a Page TSC Deadline Not Armed While in APIC Legacy Mode PCIe* Upstream TCfgWr May Cause Unpredictable System Behavior Processor May Fail to Acknowledge a TLP Request Executing The GETSEC Instruction While Throttling May Result in a Processor Hang PerfMon Event LOAD_HIT_PRE.SW_PREFETCH May Overcount Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM Exception Unexpected #UD on VPEXTRD/VPINSRD Erratum Removed Successive Fixed Counter Overflows May be Discarded #GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch Instructions A Read from The APIC-Timer CCR May Disarm The TSC_Deadline Counter An Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2 RDMSR From The APIC-Timer CCR May Disarm The APIC Timer in TSC Deadline Mode RC6 Entry Can be Blocked by Asynchronous Intel® VT-d Flows Repeated PCIe* and/or DMI L1 Transitions During Package Power States May Cause a System Hang Execution of BIST During Cold RESET Will Result in a Machine Check Shutdown PCI Express* Differential Peak-Peak Tx Voltage Swing May Violate the Specification 12 Specification Update