Intel E6320 Specification Update - Page 57

The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is

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 •MEM_UOP_RETIRED.STORES •MEM_UOP_RETIRED.LOCK •MEM_UOP_RETIRED.SPLIT •MEM_UOP_RETIRED.STLB_MISS •MEM_LOAD_UOPS_RETIRED.HIT_LFB •MEM_LOAD_UOPS_RETIRED.L1_HIT •MEM_LOAD_UOPS_RETIRED.L2_HIT •MEM_LOAD_UOPS_RETIRED.LLC_HIT •MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS •MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT •MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM •MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS •MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE •MEM_LOAD_UOPS_RETIRED.LLC_MISS •MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM •MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM •MEM_LOAD_UOPS_RETIRED.L2_MISS Implication: Due to this erratum, certain performance monitoring event will produce unreliable results during hyper-threaded operation. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BJ123. Problem: The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated After a UC Error is Logged When a UC (uncorrected) error is logged in the IA32_MC0_STATUS MSR (401H), corrected errors will continue to update the lower 14 bits (bits 51:38) of the Corrected Error Count. Due to this erratum, the sticky count overflow bit (bit 52) of the Corrected Error Count will not get updated after a UC error is logged. Implication: The Corrected Error Count Overflow indication will be lost if the overflow occurs after an uncorrectable error has been logged. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BJ124. Spurious Intel® VT-d Interrupts May Occur When the PFO Bit is Set Problem: When the PFO (Primary Fault Overflow) field (bit [0] in the VT-d FSTS [Fault Status] register) is set to 1, further faults should not generate an interrupt. Due to this erratum, further interrupts may still occur. Implication: Unexpected Invalidation Queue Error interrupts may occur. Intel has not observed this erratum with any commercially available software. Workaround: Software should be written to handle spurious Intel® VT-d fault interrupts. Status: For the steppings affected, see the Summary Tables of Changes. Specification Update 57

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Specification Update
57
•
MEM_UOP_RETIRED.STORES
•
MEM_UOP_RETIRED.LOCK
•
MEM_UOP_RETIRED.SPLIT
•
MEM_UOP_RETIRED.STLB_MISS
•
MEM_LOAD_UOPS_RETIRED.HIT_LFB
•
MEM_LOAD_UOPS_RETIRED.L1_HIT
•
MEM_LOAD_UOPS_RETIRED.L2_HIT
•
MEM_LOAD_UOPS_RETIRED.LLC_HIT
•
MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS
•
MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
•
MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
•
MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS
•
MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
•
MEM_LOAD_UOPS_RETIRED.LLC_MISS
•
MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM
•
MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM
•
MEM_LOAD_UOPS_RETIRED.L2_MISS
Implication:
Due to this erratum, certain performance monitoring event will produce unreliable
results during hyper-threaded operation.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ123.
The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not
Updated After a UC Error is Logged
Problem:
When a UC (uncorrected) error is logged in the IA32_MC0_STATUS MSR (401H),
corrected errors will continue to update the lower 14 bits (bits 51:38) of the Corrected
Error Count. Due to this erratum, the sticky count overflow bit (bit 52) of the Corrected
Error Count will not get updated after a UC error is logged.
Implication:
The Corrected Error Count Overflow indication will be lost if the overflow occurs after an
uncorrectable error has been logged.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ124.
Spurious Intel
®
VT-d Interrupts May Occur When the PFO Bit is Set
Problem:
When the PFO (Primary Fault Overflow) field (bit [0] in the VT-d FSTS [Fault Status]
register) is set to 1, further faults should not generate an interrupt. Due to this
erratum, further interrupts may still occur.
Implication:
Unexpected Invalidation Queue Error interrupts may occur. Intel has not observed this
erratum with any commercially available software.
Workaround:
Software should be written to handle spurious Intel
®
VT-d fault interrupts.
Status:
For the steppings affected, see the Summary Tables of Changes.