Intel E6320 Specification Update - Page 52

The Value in IA32_MC3_ADDR MSR May Not be Accurate When, MSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate

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Page 52 highlights

BJ103. Performance Monitor Precise Instruction Retired Event May Present Wrong Indications Problem: When the PDIR (Precise Distribution for Instructions Retired) mechanism is activated (INST_RETIRED.ALL (event C0H, umask value 00H) on Counter 1 programmed in PEBS mode), the processor may return wrong PEBS/PMI interrupts and/or incorrect counter values if the counter is reset with a SAV below 100 (Sample-After-Value is the counter reset value software programs in MSR IA32_PMC1[47:0] in order to control interrupt frequency). Implication: Due to this erratum, when using low SAV values, the program may get incorrect PEBS or PMI interrupts and/or an invalid counter state. Workaround: The sampling driver should avoid using SAV

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52
Specification Update
BJ103.
Performance Monitor Precise Instruction Retired Event May Present
Wrong Indications
Problem:
When the PDIR (Precise Distribution for Instructions Retired) mechanism is activated
(INST_RETIRED.ALL (event C0H, umask value 00H) on Counter 1 programmed in PEBS
mode), the processor may return wrong PEBS/PMI interrupts and/or incorrect counter
values if the counter is reset with a SAV below 100 (Sample-After-Value is the counter
reset value software programs in MSR IA32_PMC1[47:0] in order to control interrupt
frequency).
Implication:
Due to this erratum, when using low SAV values, the program may get incorrect PEBS
or PMI interrupts and/or an invalid counter state.
Workaround:
The sampling driver should avoid using SAV<100.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ104.
The Value in IA32_MC3_ADDR MSR May Not be Accurate When
MCACOD 0119H is Reported in IA32_MC3_Status
Problem:
Under certain conditions, when the The Machine Check Error Code (MCACOD) in the
IA32_MC3_STATUS (MSR 040DH) register is 0119H, the value in IA32_MC3_ADDR MSR
(40EH) may refer to the incoming MLC (Mid-Level Cache) cache line instead of the
evicted cache line.
Implication:
The address in IA32_MC3_ADDR MSR (40EH) may not be accurate for MLC cache read
errors with MSCOD of 119H.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ105.
MSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate
Problem:
If the processor is in a package C-state for an extended period of time (greater than 40
seconds) with no wake events, the value in the MSR_PKG_C{2,3,6,7}_RESIDENCY
MSRs (60DH and 3F8H–3FAH) will not be accurate.
Implication:
Utilities that report C-state residency times will report incorrect data in cases of long
duration package C-states.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ106.
Enabling/Disabling PEBS May Result in Unpredictable System
Behavior
Problem:
Under certain conditions, enabling or disabling PEBS (Precise Event Based Sampling)
via WRMSR to IA32_PEBS_ENABLE MSR may result in unpredictable system behavior
near or coincident to this instruction.
Implication:
Due to this erratum, unpredictable system behavior may result.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ107.
Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value
for VEX.vvvv May Produce a #NM Exception
Problem:
The VAESIMC and VAESKEYGENASSIST instructions should produce a #UD (Invalid-
Opcode) exception if the value of the vvvv field in the VEX prefix is not 1111b. Due to
this erratum, if CR0.TS is “1”, the processor may instead produce a #NM (Device-Not-
Available) exception.