Intel E6320 Specification Update - Page 48

BJ91. Some Performance Monitoring Events in AnyThread Mode May Get Incorrect Count Problem: Performance monitoring AnyThread mode allows a given thread to monitor events as a result of any thread running on the same core. Due to this erratum, on systems with SMT enabled, counting any of the following performance monitoring events in AnyThread mode may get incorrect values: •INST_RETIRED; •OTHER_ASSISTS; •UOPS_RETIRED; •MACHINE_CLEARS; •BR_INST_RETIRED; •BR_MISP_RETIRED; •SIMD_INST_RETIRED; •FP_ASSIST; •HW_INTERRUPTS; •ROB_MISC_EVENTS; •MEM_LOAD_RETIRED; •MEM_LOAD_LLC_HIT_RETIRED; •MEM_LOAD_LLC_MISS_RETIRED; •MEM_LOAD_MISC_RETIRED; Implication: Incorrect results when counting the above performance monitoring events in AnyThread mode with SMT on. Workaround: In order to get a correct count for the above events, software may count the same event on both threads of the same physical core, and at post-processing stage sum-up the two values to get the core's net value. Status: For the steppings affected, see the Summary Tables of Changes. BJ92. PDIR May Not Function Properly With FREEZE_PERFMON_ON_PMI Problem: When the PDIR (Precise Distribution for Instructions Retired) mechanism is activated (INST_RETIRED.ALL (event C0H, umask value 00H) on Counter 1 programmed in PEBS mode) along with FREEZE_PERFMON_ON_PMI, bit 11, in the IA32_DEBUGCTL MSR (1D9h), the processor may behave in an undefined manner. Implication: Due to this erratum when FREEZE_PERFMON_ON_PMI is programmed along with PDIR the processor behavior is undefined. This can result in any of but not limited to the following: incorrect PMI interrupts, incorrect PEBS events or invalid processor state. Workaround: A software driver should not program FreezeOnPMI in conjunction with the PDIR mechanism. Status: For the steppings affected, see the Summary Tables of Changes. 48 Specification Update