Intel E6320 Specification Update - Page 51

PEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full

Get Intel E6320 - Core 2 Duo Dual-Core Processor PDF manuals and user guides
UPC - 735858192576
View all Intel E6320 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 51 highlights

 BJ100. Use of VMASKMOV to Access Memory Mapped I/O or Uncached Memory May Cause The Logical Processor to Hang Problem: Under a complex set of conditions, using VMASKMOV to reference memory mapped I/O or uncached memory may cause the logical processor to hang. Implication: Due to this erratum, the logical processor may hang. Intel's Software Developers Manual states "VMASKMOV should not be used to access memory mapped I/O and uncached memory as the access and the ordering of the individual loads or stores it does is implementation specific." Intel has not observed this erratum with any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. BJ101. PEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full Problem: The Software Developer's Manual states that no PMI should be generated when PEBS index reaches PEBS Absolute Maximum. Due to this erratum a PMI may be generated even though the PEBS buffer is full. Implication: PEBS may trigger a PMI even though the PEBS index has reached the PEBS Absolute Maximum. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BJ102. XSAVEOPT May Fail to Save Some State after Transitions Into or Out of STM Problem: The XSAVEOPT instruction may optimize performance by not saving state that has not been modified since the last execution of XRSTOR. This optimization should occur only if the executions of XSAVEOPT and XRSTOR are either both or neither in SMM (systemmanagement mode). Due to this erratum, this optimization may be performed by the first execution of XSAVEOPT after a transition into or out of the STM (SMM-transfer monitor) if the most recent execution of XRSTOR occurred before that transition. For transitions into the STM, the erratum applies only to transitions using the VMCALL instruction. This erratum can occur only if the two executions are at the same privilege level, use the same linear address, and are either both or neither in VMX non-root operation. The erratum does not apply if software in SMM never uses XRSTOR or XSAVEOPT. Implication: This erratum may lead to unpredictable system behavior. Workaround: STM software should execute the XRSTOR instruction with the value 0 in EDX:EAX after each transition into the STM (after setting CR4.OSXSAVE) and before each transition out of the STM. Bytes 512 to 575 of the save area used by XRSTOR should be allocated in memory, but bytes 0 to 511 need not be. Bytes 512 to 535 should all be 0. Status: For the steppings affected, see the Summary Tables of Changes. Specification Update 51

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
Specification Update
51
BJ100.
Use of VMASKMOV to Access Memory Mapped I/O or Uncached
Memory May Cause The Logical Processor to Hang
Problem:
Under a complex set of conditions, using VMASKMOV to reference memory mapped I/O
or uncached memory may cause the logical processor to hang.
Implication:
Due to this erratum, the logical processor may hang. Intel's Software Developers
Manual states “VMASKMOV should not be used to access memory mapped I/O and un-
cached memory as the access and the ordering of the individual loads or stores it does
is implementation specific.” Intel has not observed this erratum with any commercially
available software.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ101.
PEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full
Problem:
The Software Developer’s Manual states that no PMI should be generated when PEBS
index reaches PEBS Absolute Maximum. Due to this erratum a PMI may be generated
even though the PEBS buffer is full.
Implication:
PEBS may trigger a PMI even though the PEBS index has reached the PEBS Absolute
Maximum.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ102.
XSAVEOPT May Fail to Save Some State after Transitions Into or Out
of STM
Problem:
The XSAVEOPT instruction may optimize performance by not saving state that has not
been modified since the last execution of XRSTOR. This optimization should occur only
if the executions of XSAVEOPT and XRSTOR are either both or neither in SMM (system-
management mode). Due to this erratum, this optimization may be performed by the
first execution of XSAVEOPT after a transition into or out of the STM (SMM-transfer
monitor) if the most recent execution of XRSTOR occurred before that transition. For
transitions into the STM, the erratum applies only to transitions using the VMCALL
instruction. This erratum can occur only if the two executions are at the same privilege
level, use the same linear address, and are either both or neither in VMX non-root
operation. The erratum does not apply if software in SMM never uses XRSTOR or
XSAVEOPT.
Implication:
This erratum may lead to unpredictable system behavior.
Workaround:
STM software should execute the XRSTOR instruction with the value 0 in EDX:EAX after
each transition into the STM (after setting CR4.OSXSAVE) and before each transition
out of the STM. Bytes 512 to 575 of the save area used by XRSTOR should be allocated
in memory, but bytes 0 to 511 need not be. Bytes 512 to 535 should all be 0.
Status:
For the steppings affected, see the Summary Tables of Changes.