Intel E6320 Specification Update - Page 49

For A Single Logical Processor Package, HTT May be Set to Zero Even

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 BJ93. For A Single Logical Processor Package, HTT May be Set to Zero Even Though The Package Reserves More Than One APIC ID Problem: When maximum number of addressable IDs for logical processors in this physical package (CPUID.01H.EBX[23:16]) and maximum number of addressable IDs for processor cores in the physical package, (CPUID.04H.EAX[31:26]) indicate more than one reserved APIC ID, HTT (Multi-Threading, CPUID.01H.EDX[28]) should be set to One. However, due to this erratum, it may be set to Zero. Implication: Software written expecting HTT to be Zero only when a single APIC ID is reserved for the package may not function correctly. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. BJ94. LBR May Contain Incorrect Information When Using FREEZE_LBRS_ON_PMI Problem: When FREEZE_LBRS_ON_PMI is enabled (bit 11 of IA32_DEBUGCTL MSR (1D9H) is set), and a taken branch retires at the same time that a PMI (Performance Monitor Interrupt) occurs, then under certain internal conditions the record at the top of the LBR stack may contain an incorrect "From" address. Implication: When the LBRs are enabled with FREEZE_LRBS_ON_PMI, the "From" address at the top of the LBR stack may be incorrect. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. BJ95. A First Level Data Cache Parity Error May Result in Unexpected Behavior Problem: When a load occurs to a first level data cache line resulting in a parity error in close proximity to other software accesses to the same cache line and other locked accesses the processor may exhibit unexpected behavior. Implication: Due to this erratum, unpredictable system behavior may occur. Intel has not observed this erratum with any commercially available system. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BJ96. Intel® Trusted Execution Technology ACM Revocation Problem: SINIT ACM 2nd_gen_i5_i7_SINIT_1.9.BIN or earlier are revoked and will not launch with new processor configuration information. Implication: Due to this erratum, 2nd_gen_i5_i7_SINIT_1.9.BIN and earlier will be revoked. Workaround: It is possible for the BIOS to contain a workaround for this erratum. All Intel® TXT enabled software must use SINIT ACM 2nd_gen_i5_i7_SINIT_1.9.BIN or later. Status: For the steppings affected, see the Summary Tables of Changes. Specification Update 49

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Specification Update
49
BJ93.
For A Single Logical Processor Package, HTT May be Set to Zero Even
Though The Package Reserves More Than One APIC ID
Problem:
When maximum number of addressable IDs for logical processors in this physical
package (CPUID.01H.EBX[23:16]) and maximum number of addressable IDs for
processor cores in the physical package, (CPUID.04H.EAX[31:26]) indicate more than
one reserved APIC ID, HTT (Multi-Threading, CPUID.01H.EDX[28]) should be set to
One. However, due to this erratum, it may be set to Zero.
Implication:
Software written expecting HTT to be Zero only when a single APIC ID is reserved for
the package may not function correctly.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ94.
LBR May Contain Incorrect Information When Using
FREEZE_LBRS_ON_PMI
Problem:
When FREEZE_LBRS_ON_PMI is enabled (bit 11 of IA32_DEBUGCTL MSR (1D9H) is
set), and a taken branch retires at the same time that a PMI (Performance Monitor
Interrupt) occurs, then under certain internal conditions the record at the top of the
LBR stack may contain an incorrect “From” address.
Implication:
When the LBRs are enabled with FREEZE_LRBS_ON_PMI, the “From” address at the top
of the LBR stack may be incorrect.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ95.
A First Level Data Cache Parity Error May Result in Unexpected
Behavior
Problem:
When a load occurs to a first level data cache line resulting in a parity error in close
proximity to other software accesses to the same cache line and other locked accesses
the processor may exhibit unexpected behavior.
Implication:
Due to this erratum, unpredictable system behavior may occur. Intel has not observed
this erratum with any commercially available system.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ96.
Intel® Trusted Execution Technology ACM Revocation
Problem:
SINIT ACM 2nd_gen_i5_i7_SINIT_1.9.BIN
or earlier are revoked and will not launch
with new processor configuration information.
Implication:
Due to this erratum, 2nd_gen_i5_i7_SINIT_1.9.BIN
and earlier will be revoked.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum. All Intel
®
TXT
enabled software must use SINIT ACM 2nd_gen_i5_i7_SINIT_1.9.BIN
or later.
Status:
For the steppings affected, see the Summary Tables of Changes.