Intel E6320 Specification Update - Page 13

 Errata (Sheet 4 of 5) Number BJ83 Steppings D-2 Q-0 X X Status No Fix BJ84 X X No Fix BJ85 X X No Fix BJ86 X X No Fix BJ87 X X No Fix BJ88 X X No Fix BJ89 X BJ90 X BJ91 X BJ92 X BJ93 X BJ94 X BJ95 X BJ96 X BJ97 X BJ98 X BJ99 X BJ100 X BJ101 X BJ102 X BJ103 X X No Fix X No Fix X No Fix X No Fix X No Fix X No Fix x No Fix X No Fix X Plan Fix X No Fix X No Fix X No Fix X No Fix X No Fix X No Fix BJ104 X X No Fix BJ105 X X No Fix BJ106 X No Fix BJ107 X No Fix BJ108 X BJ109 X No Fix No Fix BJ110 X X No Fix ERRATA PCIe* Presence Detect State May Not be Accurate After a Warm Reset Display Corruption May be Seen After Graphics Voltage Rail (VCC_AXG) Power Up PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate with 32-bit Length Registers VM Entries That Return From SMM Using VMLAUNCH May Not Update The Launch State of the VMCS Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered An Unexpected Page Fault May Occur Following the Unmapping and Re-mapping of a Page A PCIe* Device That Initially Transmits Minimal Posted Data Credits May Cause a System Hang Some Model Specific Branch Events May Overcount Some Performance Monitoring Events in AnyThread Mode May Get Incorrect Count PDIR May Not Function Properly With FREEZE_PERFMON_ON_PMI For A Single Logical Processor Package, HTT May be Set to Zero Even Though The Package Reserves More Than One APIC ID LBR May Contain Incorrect Information When Using FREEZE_LBRS_ON_PMI A First Level Data Cache Parity Error May Result in Unexpected Behavior Intel® Trusted Execution Technology ACM Revocation Programming PDIR And an Additional Precise PerfMon Event May Cause Unexpected PMI or PEBS Events Performance Monitoring May Overcount Some Events During Debugging LTR Message is Not Treated as an Unsupported Request Use of VMASKMOV to Access Memory Mapped I/O or Uncached Memory May Cause The Logical Processor to Hang PEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full XSAVEOPT May Fail to Save Some State after Transitions Into or Out of STM Performance Monitor Precise Instruction Retired Event May Present Wrong Indications The Value in IA32_MC3_ADDR MSR May Not be Accurate When MCACOD 0119H is Reported in IA32_MC3_Status MSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate Enabling/Disabling PEBS May Result in Unpredictable System Behavior Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for VEX.vvvv May Produce a #NM Exception Unexpected #UD on VZEROALL/VZEROUPPER Successive Fixed Counter Overflows May be Discarded Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM Exception Specification Update 13