Intel E6320 Specification Update - Page 41

 BJ65. Problem: An Unexpected Page Fault or EPT Violation May Occur After Another Logical Processor Creates a Valid Translation for a Page An unexpected page fault (#PF) or EPT violation may occur for a page under the following conditions: •The paging structures initially specify no valid translation for the page. •Software on one logical processor modifies the paging structures so that there is a valid translation for the page (e.g., by setting to 1 the present bit in one of the pagingstructure entries used to translate the page). •Software on another logical processor observes this modification (e.g., by accessing a linear address on the page or by reading the modified paging-structure entry and seeing value 1 for the present bit). •Shortly thereafter, software on that other logical processor performs a store to a linear address on the page. In this case, the store may cause a page fault or EPT violation that indicates that there is no translation for the page (e.g., with bit 0 clear in the page-fault error code, indicating that the fault was caused by a not-present page). Intel has not observed this erratum with any commercially available software. Implication: An unexpected page fault may be reported. There are no other side effects due to this erratum. Workaround: System software can be constructed to tolerate these unexpected page faults. See Section "Propagation of Paging-Structure Changes to Multiple Processors" of Volume 3A of IA-32 Intel® Architecture Software Developer's Manual, for recommendations for software treatment of asynchronous paging-structure updates. Status: For the steppings affected, see the Summary Tables of Changes. BJ66. TSC Deadline Not Armed While in APIC Legacy Mode Problem: Under specific timing conditions, when in Legacy APIC Mode, writing to IA32_TSC_DEADLINE MSR (6E0H) may fail to arm the TSC Deadline (Time Stamp Counter Deadline) event as expected. Exposure to this erratum is dependent on the proximity of TSC_Deadline MSR Write to a Timer CCR register read or to a write to the Timer LVT that enabled the TSC Deadline mode (writing 10 to bits [18:17] of Timer LVT). Implication: Due to this erratum the expected timer event will either not be generated or will be generated at a wrong time. The TSC Deadline may fail until an LVT write to transition from "TSC Deadline mode" back to "Timer mode" occurs or until the next reset. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. BJ67. PCIe* Upstream TCfgWr May Cause Unpredictable System Behavior Problem: TCfgWr (Trusted Configuration Writes) is a PCIe Base spec deprecated transaction type which should be treated as a malformed packet. If a PCIe upstream TCfgWr request is received, then due to this erratum the request may not be managed as a Malformed Packet. Implication: Upstream memory writes subsequent to a TCfgWr transaction may cause unpredictable system behavior. Intel has not observed any PCIe Device that sends such a TCfgWr request. Workaround: PCIe end points should not initiate upstream TCfgWr requests. Status: For the steppings affected, see the Summary Tables of Changes. Specification Update 41