Intel E6320 Specification Update - Page 43

A Read from The APIC-Timer CCR May Disarm The TSC_Deadline

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Page 43 highlights

 BJ72. Unexpected #UD on VPEXTRD/VPINSRD Problem: Execution of the VPEXTRD or VPINSRD instructions outside of 64-bit mode with VEX.W set to 1 may erroneously cause a #UD (invalid-opcode exception). Implication: The affected instructions may produce unexpected invalid-opcode exceptions outside 64-bit mode. Workaround: Software should encode VEX.W = 0 for executions of the VPEXTRD and VPINSRD instructions outside 64-bit mode. Status: For the steppings affected, see the Summary Tables of Changes. BJ73. Erratum Removed BJ74. Successive Fixed Counter Overflows May be Discarded Problem: Under specific internal conditions, when using Freeze PerfMon on PMI feature (bit 12 in IA32_DEBUGCTL.Freeze_PerfMon_on_PMI, MSR 1D9H), if two or more PerfMon Fixed Counters overflow very closely to each other, the overflow may be mishandled for some of them. This means that the counter's overflow status bit (in MSR_PERF_GLOBAL_STATUS, MSR 38EH) may not be updated properly; additionally, PMI interrupt may be missed if software programs a counter in Sampling-Mode (PMI bit is set on counter configuration). Implication: Successive Fixed Counter overflows may be discarded when Freeze PerfMon on PMI is used. Workaround: Software can avoid this by: •Avoid using Freeze PerfMon on PMI bit. •Enable only one fixed counter at a time when using Freeze PerfMon on PMI. Status: For the steppings affected, see the Summary Tables of Changes. BJ75. #GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch Instructions Problem: When a 2-byte opcode of a conditional branch (opcodes 0F8xH, for any value of x) instruction resides in 16-bit code-segment and is associated with invalid VEX prefix, it may sometimes signal a #GP fault (illegal instruction length > 15-bytes) instead of a #UD (illegal opcode) fault. Implication: Due to this erratum, #GP fault instead of a #UD may be signaled on an illegal instruction. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. BJ76. A Read from The APIC-Timer CCR May Disarm The TSC_Deadline Counter Problem: When in TSC Deadline mode with TSC_Deadline timer armed (IA32_TSC_DEADLINE0, MSR 6E0H), a read from the local APIC's CCR (current count register) using RDMSR 0839H may disarm the TSC Deadline timer without generating an interrupt as specified in the APIC Timer LVT (Local Vector Table) entry. Implication: Due to this erratum, unexpected disarming of the TSC_Deadline counter and possible loss of an interrupt may occur. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. Specification Update 43

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Specification Update
43
BJ72.
Unexpected #UD on VPEXTRD/VPINSRD
Problem:
Execution of the VPEXTRD or VPINSRD instructions outside of 64-bit mode with VEX.W
set to 1 may erroneously cause a #UD (invalid-opcode exception).
Implication:
The affected instructions may produce unexpected invalid-opcode exceptions outside
64-bit mode.
Workaround:
Software should encode VEX.W = 0 for executions of the VPEXTRD and VPINSRD
instructions outside 64-bit mode.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ73.
Erratum Removed
BJ74.
Successive Fixed Counter Overflows May be Discarded
Problem:
Under specific internal conditions, when using Freeze PerfMon on PMI feature (bit 12 in
IA32_DEBUGCTL.Freeze_PerfMon_on_PMI, MSR 1D9H), if two or more PerfMon Fixed
Counters overflow very closely to each other, the overflow may be mishandled for some
of them. This means that the counter’s overflow status bit (in
MSR_PERF_GLOBAL_STATUS, MSR 38EH) may not be updated properly; additionally,
PMI interrupt may be missed if software programs a counter in Sampling-Mode (PMI bit
is set on counter configuration).
Implication:
Successive Fixed Counter overflows may be discarded when Freeze PerfMon on PMI is
used.
Workaround:
Software can avoid this by:
•
Avoid using Freeze PerfMon on PMI bit.
•
Enable only one fixed counter at a time when using Freeze PerfMon on PMI.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ75.
#GP May be Signaled When Invalid VEX Prefix Precedes Conditional
Branch Instructions
Problem:
When a 2-byte opcode of a conditional branch (opcodes 0F8xH, for any value of x)
instruction resides in 16-bit code-segment and is associated with invalid VEX prefix, it
may sometimes signal a #GP fault (illegal instruction length > 15-bytes) instead of a
#UD (illegal opcode) fault.
Implication:
Due to this erratum, #GP fault instead of a #UD may be signaled on an illegal
instruction.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ76.
A Read from The APIC-Timer CCR May Disarm The TSC_Deadline
Counter
Problem:
When in TSC Deadline mode with TSC_Deadline timer armed
(IA32_TSC_DEADLINE<>0, MSR 6E0H), a read from the local APIC’s CCR (current
count register) using RDMSR 0839H may disarm the TSC Deadline timer without
generating an interrupt as specified in the APIC Timer LVT (Local Vector Table) entry.
Implication:
Due to this erratum, unexpected disarming of the TSC_Deadline counter and possible
loss of an interrupt may occur.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.