Intel H2000WP Technical Product Specification - Page 31

Intel® Server Chassis H2000 Family TPS Power Sub-System 3.3.12 Zero Load Stability Requirement When the power subsystem operates in a no load condition, it does not need to meet the output regulation specification, but it must operate without any tripping of over-voltage or other fault circuitry. When the power subsystem is subsequently loaded, it must begin to regulate and source current without fault. 3.3.13 Hot Swap Requirement Hot swapping a power supply is the process of inserting and extracting a power supply from an operating power system. During this process the output voltages shall remain within the limits with the capacitive load specified. The hot swap test must be conducted when the system is operating under static, dynamic, and zero loading conditions. The power supply shall use a latching mechanism to prevent insertion and extraction of the power supply when the AC power cord is inserted into the power supply. 3.3.14 Forced Load Sharing The +12V output will have active load sharing. The output will share within 10% at full load. The failure of a power supply should not affect the load sharing or output voltages of the other supplies still operating. The supplies must be able to load share in parallel and operate in a hotswap/redundant 1+1 configurations. The 12VSBoutput is not required to actively share current between power supplies (passive sharing). The 12VSBoutput of the power supplies are connected together in the system so that a failure or hot swap of a redundant power supply does not cause these outputs to go out of regulation in the system. 3.3.15 Timing Requirement These are the timing requirements for the power supply operation. The output voltages must rise from 10% to within regulation limits (Tvout_rise) within 5 to 70ms. For 12VSB, it is allowed to rise from 1.0 to 25ms. All outputs must rise monotonically. Table below shows the timing requirements for the power supply being turned on and off through the AC input, with PSON held low and the PSON signal, with the AC input applied. Table 24. Timing Requirement Item Tvout_rise T sb_on_delay T ac_on_delay T vout_holdup T pwok_holdup T pson_on_delay T pson_pwok T pwok_on Description Output voltage rise time Delay from AC being applied to 12VSBbeing within regulation. Delay from AC being applied to all output voltages being within regulation. Time 12Vl output voltage stay within regulation after loss of AC. Delay from loss of AC to de-assertion of PWOK Delay from PSON# active to output voltages within regulation limits. Delay from PSON# deactivate to PWOK being de-asserted. Delay from output voltages within regulation limits to PWOK Min. 5.0 * 13 10.6 5 100 Max. 70 * 1500 3000 400 5 500 Units ms ms ms ms ms ms ms ms Revision 1.0 21 Intel order number: G59059-001