Intel H2000WP Technical Product Specification - Page 36

Over Thermal protection, PMBus, PSU Address Lines A0

Page 36 highlights

Power Sub-System Intel® Server Chassis H2000 Family TPS 3.6.3 Over Thermal protection The power supply will be protected against over temperature conditions caused by loss of fan cooling or excessive ambient temperature. In an OTP condition the PSU will shut down. When the power supply temperature drops to within specified limits, the power supply shall restore power automatically, while the 12VSB remains always on. The OTP circuit must have built in margin such that the power supply will not oscillate on and off due to temperature recovering condition. The OTP trip level shall have a minimum of 4C of ambient temperature margin. 3.7 PMBus* The PMBus* features are requirements for power supply unit for use in server systems. This specification is based on the PMBus* specifications part I and II, revision 1.1. The power supply device address locations are shown below: Figure 13. Power Supply Device Address The PMBus* from PDB is connected to BMC of all four nodes. Only one board BMC is assigned to be the master BMC and communicate with PSU as single point. Other board BMCs are getting PSU data from the master BMC. In case the master BMC is down, one of the slave board BMC will be promoted automatically as master BMC and maintain the communication. 3.7.1 PSU Address Lines A0 Address pins A0 is used by end use system to allocate unit address to a power supply in particular slot position. For redundant systems there are two signals to set the address location of the power supply once it is installed in the system; Address0 and Address1. For non-redundant systems the power supply device address locations should align with the Address0/Address1 location of 0/0. 26 Revision 1.0 Intel order number: G59059-001

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Power Sub-System
Intel
®
Server Chassis H2000 Family TPS
Revision 1.0
Intel order number: G59059-001
26
3.6.3
Over Thermal protection
The power supply will be protected against over temperature conditions caused by loss of fan
cooling or excessive ambient temperature. In an OTP condition the PSU will shut down. When
the power supply temperature drops to within specified limits, the power supply shall restore
power automatically, while the 12VSB remains always on. The OTP circuit must have built in
margin such that the power supply will not oscillate on and off due to temperature recovering
condition. The OTP trip level shall have a minimum of 4
C of ambient temperature margin.
3.7
PMBus*
The PMBus* features are requirements for power supply unit for use in server systems. This
specification is based on the
PMBus* specifications part I and II, revision 1.1
. The power supply
device address locations are shown below:
Figure 13. Power Supply Device Address
The PMBus* from PDB is connected to BMC of all four nodes. Only one board BMC is assigned
to be the master BMC and communicate with PSU as single point. Other board BMCs are
getting PSU data from the master BMC. In case the master BMC is down, one of the slave
board BMC will be promoted automatically as master BMC and maintain the communication.
3.7.1
PSU Address Lines A0
Address pins A0 is used by end use system to allocate unit address to a power supply in
particular slot position.
For redundant systems there are two signals to set the address location of the power supply
once it is installed in the system; Address0 and Address1. For non-redundant systems the
power supply device address locations should align with the Address0/Address1 location of 0/0.