Intel H2000WP Technical Product Specification - Page 54
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Intel® Server Chassis H2000 Family TPS Glossary Term ACPI AP APIC ASIC ASMI BIOS BIST BMC Bridge BSP Byte CBC CEK CHAP CMOS DPC EEPROM EHCI EMP EPS ESB2-E FBD FMB FRB FRU FSB GB GPIO GTL HSC Hz I2C IA IBF ICH ICMB IERR IFB INTR Glossary Definition Advanced Configuration and Power Interface Application Processor Advanced Programmable Interrupt Control Application Specific Integrated Circuit Advanced Server Management Interface Basic Input/Output System Built-In Self Test Baseboard Management Controller Circuitry connecting one computer bus to another, allowing an agent on one to access the other Bootstrap Processor 8-bit quantity. Chassis Bridge Controller (A microcontroller connected to one or more other CBCs, together they bridge the IPMB buses of multiple chassis.) Common Enabling Kit Challenge Handshake Authentication Protocol In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytes of memory, which normally resides on the server board Direct Platform Control Electrically Erasable Programmable Read-Only Memory Enhanced Host Controller Interface Emergency Management Port External Product Specification Enterprise South Bridge 2 Fully Buffered DIMM Flexible Mother Board Fault Resilient Booting Field Replaceable Unit Front Side Bus 1024MB General Purpose I/O Gunning Transceiver Logic Hot-Swap Controller Hertz (1 cycle/second) Inter-Integrated Circuit Bus Intel® Architecture Input Buffer I/O Controller Hub Intelligent Chassis Management Bus Internal Error I/O and Firmware Bridge Interrupt 44 Revision 1.0 Intel order number: G59059-001