Intel P4000RP Technical Product Specification - Page 124
Intel SMX Safer Mode Extensions
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BIOS Setup Interface Intel® Server Board S1200V3RP Disabled Help Text: The next cache line will be prefetched into L1 instruction cache from L2 or system memory during unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache line as data. Comments: DCU Data Prefetcher is normally Enabled, for best efficiency in L1 Instruction Cache and Memory Channel use but disabling it may improve performance for some processing loads and on certain benchmarks. Back to [Advanced Screen] - [Screen Map] 27. Intel (SMX) Safer Mode Extensions Option Values: Enabled Disabled Help Text: When Enabled, a SMX can utilize the additional hardware capabilities provided by Safer Mode Extensions. Comments: Back to [Advanced Screen] - [Screen Map] 28. SMM Wait Timeout Option Values: [Entry Field 20 - 3000ms, 20 is default] Help Text: Millisecond timeout waiting for BSP and APs to enter SMM. Range is 20ms to 3000ms. Comments: Amount of time to allow for the SMI Handler to respond to an SMI. If exceeded, BMC generates an SMI Timeout and resets the system. Note: this field is temporary, and will be removed when no longer required. Back to [Advanced Screen] - [Screen Map] 9.4.2.5 Memory Configuration The Memory Configuration screen allows the user to view details about the DDR3 DIMMs that are installed as system memory, and alter BIOS Memory Configuration settings where appropriate. 112 Revision 1.0