Intel P4000RP Technical Product Specification - Page 29

Intel® Server Board S1200V3RP Functional Architecture 3.3.1.2 Publishing System Memory  The BIOS displays the Total Memory of the system during POST if Display Logo is disabled in the BIOS setup. This is the total size of memory discovered by the BIOS during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the system.  The BIOS displays the Effective Memory of the system in the BIOS setup. The term Effective Memory refers to the total size of all DDR3 DIMMs that are active (not disabled).  The BIOS provides the total memory of the system in the main page of the BIOS setup. This total is the same as the amount described by the first bullet above.  If Display Logo is disabled, the BIOS displays the total system memory on the diagnostic screen at the end of POST. This total is the same as the amount described by the first bullet above. Note: Some server operating systems do not display the total physical memory installed. What is displayed is the amount of physical memory minus the approximate memory space used by system BIOS components. These BIOS components include, but are not limited to: 1. ACPI (may vary depending on the number of PCI devices detected in the system) 2. ACPI NVS table 3. Processor microcode 4. Memory Mapped I/O (MMIO) 5. Manageability Engine (ME) 6. BIOS flash 3.3.2 Memory RAS Features For Intel® Server Board S1200V3RP product family, the form of Memory RAS provided is Error Correction Code (ECC). ECC uses extra bits - 64-bit data in a 72-bit DRAM array - to add an 8bit calculated Hamming Code to each 64 bits of data. This additional encoding enables the memory controller to detect and report single or double bit errors, and to correct single-bit errors. There is a specific step in memory initialization in which all of memory is cleared to zeroes before the ECC function is enabled, in order to bring the ECC codes into agreement with memory contents. During operation, in the process of every fetch from memory, the data and ECC bits are examined for each 64-bit data plus 8-bit ECC group. If the ECC computation indicates that a single bit Correctable Error has occurred, it is corrected and the corrected data is passed on to the processor. If a double-bit Uncorrectable Error is detected, it cannot be corrected. In each case, a Correctable or Uncorrectable ECC Error event is generated. For Correctable Errors, there is a certain tolerance observed, since a Correctable Error can be generated by something as random as a stray Cosmic Ray impacting the DIMM. Correctable Errors are counted on a per-DIMM basis, but are just silently recorded until the tolerance threshold is crossed. The Correctable Error Threshold for Intel® Server Board S1200V3RP Revision 1.0 17