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Intel® Server Board S1200V3RP Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Se Platform ns Applicabilit or y # Sensor Type Event/R eading Type Event Offset Triggers Margin 6 (Agg Therm Mrgn 6) Global Aggregate Temperature Margin 7 (Agg Therm C E h Mrgn 7) Global Aggregate Temperature C Margin 8 F h (Agg Therm Mrgn 8) Platform Specific Platform Specific 01h 01h Temper Thresh ature old - 01h 01h Temper Thresh ature old - 01h 01h Baseboard +12V (BB +12.0V) D 0h All Voltage 02h Thresh old 01h [u,l] [c,nc] Baseboard +5V (BB +5.0V) D 1h All Voltage 02h Thresh old 01h [u,l] [c,nc] Baseboard +3.3V (BB +3.3V) D 2h All Baseboard +5V Standby (BB +5.0V STBY) D 3h All Baseboard +3.3V Auxiliary (BB +3.3V AUX) Baseboard +1.05V Processor1 Vccp (BB D 4h All D 6h All Voltage 02h Thresh old 01h [u,l] [c,nc] Voltage 02h Thresh old 01h [u,l] [c,nc] Voltage 02h Thresh old 01h [u,l] [c,nc] Voltage 02h Thresh old 01h [u,l] [c,nc] Contrib. Assert Reada Event Rearm St To /De- ble Data an System assert db Status Value/ y Offset s - - Analo g R, T A - - - Analo g R, T A - nc = Degrad ed As and c = De Analo g R, T A - Non- fatal nc = Degrad ed As and c = De Analo g R, T A - Non- fatal nc = Degrad ed c = As and De Analo g R, T A - Non- fatal nc = Degrad ed As and c = De Analo g R, T A X Non- fatal nc = Degrad ed As and c = De Analo g R, T A X Non- fatal nc = Degrad As ed and c = De Analo g R, T A - Non- Revision 1.0 229

Section	Page
1. Introduction	13
1.1 Chapter Outline	13
1.2 Server Board Use Disclaimer	13
2. Overview	15
2.1 Intel® Server Boards S1200V3RP product family Feature Set	15
2.2 Server Board Layout	17
2.2.1 Server Board Connector and Component Layout	17
2.2.2 Server Board Mechanical Drawings	20
2.2.3 Server Board Rear I/O Layout	23
3. Functional Architecture	24
3.1 Processor Subsystem	24
3.1.1 Intel® Xeon® processor E3-1200 V3 product family	25
3.1.2 The 4th Generation Intel® Core™ i3 Processors	25
3.2 Processor Function Overview	25
3.3 Integrated Memory Controller (IMC) and Memory Subsystem	26
3.3.1 Supported Memory	27
3.3.1.1 Memory Population Rules	27
3.3.1.2 Publishing System Memory	29
3.3.2 Memory RAS Features	29
3.3.3 Post Error Codes	30
3.3.4 Processor Integrated I/O Module (IIO)	30
3.3.5 Intel® Integrated RAID Option	32
3.3.6 Optional I/O Module Support	32
3.3.7 Intel® I/O Acceleration Technolgy 2 (Intel® I/O AT2)	32
3.3.7.1 Direct Cache Access (DCA)	33
3.4 Intel® C220 series Chipset PCH Functional Overview	33
3.4.1 Digital Media Interface (DMI)	34
3.4.2 PCI Express* Interface	34
3.4.3 Serial ATA (SATA) Controller	34
3.4.3.1 AHCI	34
3.4.3.2 Intel® Rapid Storage Technology enterprise	35
3.4.3.3 Intel® Embedded Server RAID Technology 2 (ESRT2)	35
3.4.4 Low Pin Count (LPC) Interface	35
3.4.5 Serial Peripheral Interface (SPI)	35
3.4.6 Universal Serial Bus (USB) Controller	36
3.4.6.1 Native USB Support	36
3.4.6.2 Legacy USB Support	36
3.4.6.3 eUSB SSD Support	37
3.4.7 Gigabit Ethernet Controller	37
3.4.7.1 MAC Address Definition	38
3.4.8 Enhanced Power Management	38
3.4.9 Serial Ports	38
3.4.10 KVM/Serial Over LAN (SOL) Function	38
3.4.11 System Management Bus (SMBus* 2.0)	38
3.4.12 Intel® Virtualization Technology for Direct I/O (Intel® VT-d)	39
3.5 Integrated Baseboard Management Controller (BMC) Overview	39
3.5.1 Super I/O Controller	40
3.5.1.1 Keyboard and Mouse Support	40
3.5.1.2 Wake-up Control	41
3.5.2 Graphics Controller and Video Support	41
3.5.3 Baseboard Management Controller	42
3.5.3.1 Remote Keyboard, Video, Mouse, and Storage (KVMS) Support	43
3.5.3.2 Integrated BMC Embedded LAN Channel	43
4. System Security	44
4.1 BIOS Password Protection	44
4.2 Trusted Platform Module (TPM) Support	45
4.2.1 TPM security BIOS	45
4.2.2 Physical Presence	46
4.2.3 TPM Security Setup Options	46
4.2.3.1 Security Screen	46
4.3 Intel® Trusted Execution Technology	48
5. Intel® Technology Support	49
5.1 Intel® Trusted Execution Technology	49
5.2 Intel® Virtualization Technology – Intel® VT-x/VT-d/VT-c	49
5.3 Intel® Intelligent Power Node Manager	50
5.3.1 Hardware Requirements	52
6. Platform Management Functional Overview	53
6.1 Baseboard Management Controller (BMC) Firmware Feature Support	53
6.1.1 IPMI 2.0 Features	53
6.1.2 Non-IPMI Features	54
6.2 Basic and Advanced Features	55
6.3 Advanced Configuration and Power Interface (ACPI)	56
6.4 Power Control Sources	57
6.5 BMC Watchdog	57
6.6 Fault Resilient Booting (FRB)	58
6.7 Sensor Monitoring	58
6.8 Field Replaceable Unit (FRU) Inventory Device	59
6.9 System Event Log (SEL)	59
6.10 System Fan Management	59
6.10.1 Thermal and Acoustic Management	59
6.10.2 Thermal Sensor Input to Fan Speed Control	60
6.10.3 Fan Profiles	61
6.10.4 Memory Thermal Throttling	62
6.11 Messaging Interfaces	63
6.11.1 User Model	63
6.11.2 IPMB Communication Interface	64
6.11.3 LAN Interface	64
6.11.3.1 RMCP/ASF Messaging	64
6.11.3.2 BMC LAN Channels	64
6.11.3.2.1 Baseboard NICs	64
6.11.3.2.2 Dedicated Management Channel	65
6.11.3.2.3 Concurrent Server Management Use of Multiple Ethernet Controllers	65
6.11.3.3 IPV6 Support	66
6.11.3.4 LAN Failover	67
6.11.3.5 BMC IP Address Configuration	67
6.11.3.5.1 Static IP Address (IP Address Source Values 0h, 1h, and 3h)	68
6.11.3.5.2 Static LAN Configuration Parameters	68
6.11.3.5.3 Enabling/Disabling Dynamic Host Configuration (DHCP) Protocol	68
6.11.3.5.4 DHCP-related LAN Configuration Parameters	69
6.11.3.6 DHCP BMC Hostname	69
6.11.4 Address Resolution Protocol (ARP)	70
6.11.5 Internet Control Message Protocol (ICMP)	70
6.11.6 Virtual Local Area Network (VLAN)	70
6.11.7 Secure Shell (SSH)	71
6.11.8 Serial-over-LAN (SOL 2.0)	71
6.11.9 Platform Event Filter (PEF)	71
6.11.10 LAN Alerting	72
6.11.10.1 SNMP Platform Event Traps (PETs)	72
6.11.11 Alert Policy Table	72
6.11.11.1 E-mail Alerting	73
6.11.12 SM-CLP (SM-CLP Lite)	73
6.11.13 Embedded Web Server	74
6.11.14 Virtual Front Panel	75
6.11.15 Embedded Platform Debug	76
6.11.15.1 Output Data Format	77
6.11.15.2 Output Data Availability	77
6.11.15.3 Output Data Categories	78
6.11.16 Data Center Management Interface (DCMI)	78
6.11.17 Lightweight Directory Authentication Protocol (LDAP)	79
7. Advanced Management Feature Support (RMM4)	80
7.1 Keyboard, Video, and Mouse (KVM) Redirection	81
7.1.1 Remote Console	82
7.1.2 Performance	83
7.1.3 Security	83
7.1.4 Availability	83
7.1.5 Usage	83
7.1.6 Force-enter BIOS Setup	83
7.2 Media Redirection	83
7.2.1 Availability	84
7.2.2 Network Port Usage	84
8. On-board Connector/Header Overview	86
8.1 Board Connector Information	86
8.2 Power Connectors	87
8.3 System Management Headers	88
8.3.1 Intel® Remote Management Module 4 Dedicated NIC Connector	88
8.3.2 TPM connector	89
8.3.3 Intel® ESRT2 RAID Upgrade Key Connector	89
8.3.4 Local Control Panel Header	89
8.3.5 HSBP_ I2C Header	90
8.3.6 HDD LED Header	90
8.3.7 Chassis Intrusion Header	90
8.3.8 SATA SGPIO Header	90
8.3.9 IPMB Connector	90
8.4 Front Panel Connector	91
8.4.1 Power/Sleep Button and LED Support	91
8.4.2 System ID Button and LED Support	92
8.4.3 System Reset Button Support	92
8.4.4 NMI Button Support	92
8.4.5 NIC Activity LED Support	93
8.4.6 Hard Drive Activity LED Support	93
8.4.7 System Status LED Support	93
8.5 I/O Connectors	93
8.5.1 VGA Connector	93
8.5.2 Display Port Connector	93
8.5.3 SATA Connectors	94
8.5.4 Serial Port Connectors	94
8.5.5 USB Connector	95
8.5.6 I/O Module Connector	96
8.5.7 SAS Module Connector	97
8.5.8 NIC1 with USB2.0 connector	98
8.5.9 NIC2 with USB3.0 connector	99
8.6 Fan Headers	100
9. BIOS Setup Interface	101
9.1 HotKeys Supported During POST	101
9.2 POST Logo/Diagnostic Screen	101
9.3 BIOS Boot Pop-up Menu	102
9.4 BIOS Setup Utility	102
9.4.1 BIOS Setup Operation	102
9.4.1.1 Setup Page Layout	103
9.4.1.2 Entering BIOS Setup	104
9.4.1.3 Setup Navigation Keyboard Commands	104
9.4.1.4 Setup Screen Menu Selection Bar	105
9.4.2 BIOS Setup Utility Screens	105
9.4.2.1 Map of Screens and Functionality	106
9.4.2.2 Main Screen (Tab)	107
9.4.2.3 Advanced Screen (Tab)	111
9.4.2.4 Processor Configuration	114
9.4.2.5 Memory Configuration	124
9.4.2.6 Mass Storage Controller Configuration	128
9.4.2.7 PCI Configuration	131
9.4.2.8 NIC Configuration	135
9.4.2.9 Serial Port Configuration	144
9.4.2.10 USB Configuration	146
9.4.2.11 System Acoustic and Performance Configuration	151
9.4.2.12 Network Stack	154
9.4.2.13 Security Screen (Tab)	155
9.4.2.14 Server Management Screen (Tab)	160
9.4.2.15 Console Redirection	168
9.4.2.16 System Information	171
9.4.2.17 BMC LAN Configuration	174
9.4.2.18 Boot Options Screen (Tab)	187
9.4.2.19 CDROM Order	194
9.4.2.20 Hard Disk Order	194
9.4.2.21 Floppy Order	195
9.4.2.22 Network Device Order	196
9.4.2.23 BEV Device Order	197
9.4.2.24 Add EFI Boot Option	198
9.4.2.25 Delete EFI Boot Option	199
9.4.2.26 Boot Manager Screen (Tab)	200
9.4.2.27 Error Manager Screen (Tab)	201
9.4.2.28 Save & Exit Screen (Tab)	202
10. Jumper Blocks	207
10.1 BIOS Default Jumper Block	208
10.2 BIOS Recovery Jumper	208
10.3 Password Clear Jumper Block	209
10.4 Management Engine (ME) Firmware Force Update Jumper Block	210
10.5 BMC Force Update Jumper Block	211
11. Intel® Light Guided Diagnostics	212
11.1 System ID LED	213
11.2 System Status LED	213
11.3 BMC Boot/Reset Status LED Indicators	215
11.4 Post Code Diagnostic LEDs	215
11.5 5 Volt Stand-By Present LED	216
12. Environmental Limits Specification	217
12.1 Processor Thermal Design Power (TDP) Support	217
12.2 MTBF	218
13. Server Board Power Distribution	219
13.1 DC Output Specification	219
13.1.1 Output Power/Currents	219
13.1.2 Cross Loading	220
13.1.3 Standby Output	220
13.1.4 Voltage Regulation	220
13.1.5 Dynamic Loading	221
13.1.6 Capacitive Loading	221
13.1.7 Grounding	221
13.1.8 Residual Voltage Immunity in Standy mode	221
13.1.9 Common Mode Noise	222
13.1.10 Ripple/Noise	222
13.1.11 Timing Requirements	222
Appendix A: Integration and Usage Tips	225
Appendix B: Integrated BMC Sensor Tables	226
Appendix C: POST Code Diagnostic LED Decoder	245
Appendix D: POST Code Errors	251
Appendix E: Supported Intel® Server Chassis	258
Glossary	259

Match case Limit results 1 per page

Intel® Server Board S1200V3RP

Appendix

B: Integrated BMC Sensor Tables

Full Sensor

Name

(Sensor name

in SDR)

Platform

Applicabilit

Sensor

Type

Event/R

eading

Type

Event Offset Triggers

Contrib.

System

Status

Assert

/De-

assert

Reada

ble

Value/

Offset

Event

Data

Rearm

Margin 6

(Agg Therm

Mrgn 6)

01h

Global

Aggregate

Temperature

Margin 7

(Agg Therm

Mrgn 7)

Platform

Specific

Temper

ature

01h

Thresh

old

01h

Analo

R, T

–

Global

Aggregate

Temperature

Margin 8

(Agg Therm

Mrgn 8)

Platform

Specific

Temper

ature

01h

Thresh

old

01h

Analo

R, T

–

Baseboard

+12V

(BB +12.0V)

All

Voltage

02h

Thresh

old

01h

[u,l] [c,nc]

nc =

Degrad

c =

Non-

fatal

and

Analo

R, T

–

Baseboard

+5V

(BB +5.0V)

All

Voltage

02h

Thresh

old

01h

[u,l] [c,nc]

nc =

Degrad

c =

Non-

fatal

and

Analo

R, T

–

Baseboard

+3.3V

(BB +3.3V)

All

Voltage

02h

Thresh

old

01h

[u,l] [c,nc]

nc =

Degrad

c =

Non-

fatal

and

Analo

R, T

–

Baseboard

+5V Stand-

(BB +5.0V

STBY)

All

Voltage

02h

Thresh

old

01h

[u,l] [c,nc]

nc =

Degrad

c =

Non-

fatal

and

Analo

R, T

Baseboard

+3.3V

Auxiliary

(BB +3.3V

AUX)

All

Voltage

02h

Thresh

old

01h

[u,l] [c,nc]

nc =

Degrad

c =

Non-

fatal

and

Analo

R, T

Baseboard

+1.05V

Processor1

Vccp

(BB

All

Voltage

02h

Thresh

old

01h

[u,l] [c,nc]

nc =

Degrad

c =

Non-

and

Analo

R, T

–

Revision 1.0

229