Asus Crosshair II Formula User Manual - Page 89

DRAM Timing Control

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Tref [Auto] Configuration options: [Auto] [7.8 us] [3.9 us] Trfc [Auto] Configuration options: [Auto] [0] [1] [2] [3] [4] Dynamic Idle Cycle Counter [Auto] Configuration options: [Auto] [Disabled] [Enabled] Idle Cycle Limit [Auto] Configuration options: [Auto] [0 cycles] [4 cycles] [8 cycles] [16 cycles] [32 cycles] [64 cycles] [128 cycles] DCQ Bypass Maximum [Auto] Configuration options: [Auto] [0x] [1x] [2x]-[14x] [15x] DRAM Burst Length [Auto] Configuration options: [Auto] [64-byte] [32-byte] DRAM Bank Interweaving [Enabled] Configuration options: [Disabled] [Enabled] Bank Swizzle Mode [Enabled] Configuration options: [Disabled] [Enabled] DRAM Timing Control CKE Fine Delay [Auto] Configuration options: [Auto] [No Delay] [1/64 MEMCLK delay] [2/64 MEMCLK delay] [3/64 MEMCLK delay]-[30/64 MEMCLK delay] [31/64 MEMCLK delay] CKE Setup Time [Auto] Configuration options: [Auto] [1/2 MEMCLK] [1 MEMCLK] CS/ODT Fine Delay [Auto] Configuration options: [Auto] [No Delay] [1/64 MEMCLK delay] [2/64 MEMCLK delay] [3/64 MEMCLK delay]-[30/64 MEMCLK delay] [31/64 MEMCLK delay] CS/ODT Setup Time [Auto] Configuration options: [Auto] [1/2 MEMCLK] [1 MEMCLK] Address/Command Fine Delay [Auto] Configuration options: [Auto] [No Delay] [1/64 MEMCLK delay] [2/64 MEMCLK delay] [3/64 MEMCLK delay]-[30/64 MEMCLK delay] [31/64 MEMCLK delay] Address/Command Setup Time [Auto] Configuration options: [Auto] [1/2 MEMCLK] [1 MEMCLK] Read DQS Timing Control [Auto] Configuration options: [Auto] [No Delay] [1/96 MEMCLK delay] [2/96 MEMCLK delay] [3/96 MEMCLK delay]-[46/96 MEMCLK delay] [47/96 MEMCLK delay] ASUS Crosshair II Formula 4-17

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ASUS Crosshair II Formula
4-17
Tref [Auto]
Configuration options: [Auto] [7.8 us] [3.9 us]
Trfc [Auto]
Configuration options: [Auto] [0] [1] [2] [3] [4]
Dynamic Idle Cycle Counter [Auto]
Configuration options: [Auto] [Disabled] [±nabled]
Idle Cycle Limit [Auto]
Configuration options: [Auto] [0 cycles] [4 cycles] [8 cycles] [16 cycles] [32 cycles]
�64 cycles± �128 cycles±
DCQ Bypass Maximum [Auto]
Configuration options: [Auto] [0x] [1x] [2x]–[14x] [15x]
DRAM Burst Length [Auto]
Configuration options: [Auto] [64�byte] [32�byte]
DRAM Bank Interweaving [Enabled]
Configuration options: [Disabled] [±nabled]
Bank Swizzle Mode [Enabled]
Configuration options: [Disabled] [±nabled]
DRAM Timing Control
CKE Fine Delay [Auto]
Configuration options: [Auto] [No Delay] [1/64 M±MCLK delay] [2/64 M±MCLK
delay± �3/64 MEMCLK delay±–�30/64 MEMCLK delay± �31/64 MEMCLK delay±
CKE Setup Time [Auto]
Configuration options: [Auto] [1/2 M±MCLK] [1 M±MCLK]
CS/ODT Fine Delay [Auto]
Configuration options: [Auto] [No Delay] [1/64 M±MCLK delay] [2/64 M±MCLK
delay± �3/64 MEMCLK delay±–�30/64 MEMCLK delay± �31/64 MEMCLK delay±
CS/ODT Setup Time [Auto]
Configuration options: [Auto] [1/2 M±MCLK] [1 M±MCLK]
Address/Command Fine Delay [Auto]
Configuration options: [Auto] [No Delay] [1/64 M±MCLK delay] [2/64 M±MCLK
delay± �3/64 MEMCLK delay±–�30/64 MEMCLK delay± �31/64 MEMCLK delay±
Address/Command Setup Time [Auto]
Configuration options: [Auto] [1/2 M±MCLK] [1 M±MCLK]
Read DQS Timing Control [Auto]
Configuration options: [Auto] [No Delay] [1/96 M±MCLK delay] [2/96 M±MCLK
delay± �3/96 MEMCLK delay±–�46/96 MEMCLK delay± �47/96 MEMCLK delay±