Dell PowerEdge M420 Dell PowerEdge M420 Systems Owner's Manual - Page 44

Operating Frequency in MT/s, Maximum DIMM Rank

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Memory bus operating frequency can be 1600 MT/s or 1333 MT/s depending on: • DIMM configuration (number of ranks) • maximum frequency of the DIMMs • DIMM operating voltage • system profile selected (for example, Performance Optimized, Custom, or Dense Configuration Optimized) • maximum supported DIMM frequency of the processors The following table shows the memory populations and operating frequencies for the supported configurations. DIMM Type DIMMs Populated/ Channel RDIMM 1 RDIMM 1 Operating Frequency (in MT/s) 1.5 V 1600 and 1333 - 1.35 V 1333 1333 Maximum DIMM Rank/ Channel Dual rank Quad rank The system contains six memory sockets split into two sets of three sockets, one set per processor. Each three-socket set is organized into three channels. NOTE: DIMMs in sockets A1 to A3 are assigned to processor 1 and DIMMs in sockets B1 to B3 are assigned to processor 2. Figure 19. Memory Socket Locations Memory channels are organized as follows: Processor 1 Processor 2 channel 1: memory socket A1 channel 2: memory socket A2 channel 3: memory socket A3 channel 1: memory socket B1 channel 2: memory socket B2 channel 3: memory socket B3 44

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Memory bus operating frequency can be 1600 MT/s or 1333 MT/s depending on:
•
DIMM configuration (number of ranks)
•
maximum frequency of the DIMMs
•
DIMM operating voltage
•
system profile selected (for example, Performance Optimized, Custom, or Dense Configuration Optimized)
•
maximum supported DIMM frequency of the processors
The following table shows the memory populations and operating frequencies for the supported configurations.
DIMM Type
DIMMs Populated/
Channel
Operating Frequency (in MT/s)
Maximum DIMM Rank/
Channel
1.5 V
1.35 V
RDIMM
1
1600 and 1333
1333
Dual rank
RDIMM
1
-
1333
Quad rank
The system contains six memory sockets split into two sets of three sockets, one set per processor. Each three-socket
set is organized into three channels.
NOTE:
DIMMs in sockets A1 to A3 are assigned to processor 1 and DIMMs in sockets B1 to B3 are assigned to
processor 2.
Figure 19. Memory Socket Locations
Memory channels are organized as follows:
Processor 1
channel 1: memory socket A1
channel 2: memory socket A2
channel 3: memory socket A3
Processor 2
channel 1: memory socket B1
channel 2: memory socket B2
channel 3: memory socket B3
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