HP ProLiant DL980 DL980 G7 User Installation Guide - Page 45

Memory RAS

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• The largest contributor to maximum memory bandwidth performance is to use both memory controllers inside the processor. To achieve maximum memory bandwidth performance, populate both memory cartridges for each installed processor. This configuration is required for this server. • The second largest contributor to performance is to populate each DDR3 channel in each memory cartridge. To achieve this, the minimum DIMM count per cartridge is four DIMMs installed in DIMM pair locations A and B. • The next largest contributor to performance is the number of ranks per DIMM. Dual-rank DIMMs perform significantly better than single-rank DIMMs. Quad-rank DIMMs offer a further performance boost. • The best performance is obtained when all installed processors are enabled for Hemisphere mode. Hemisphere mode is optimum when four or eight DIMMs are installed per cartridge. Hemisphere mode can be achieved with two or six DIMMs per cartridge (2 cartridges per processor), but this configuration is not optimal for Hemisphere mode. Hemisphere mode is required for this server. • Maximum throughput is achieved when all memory cartridges are fully populated with the maximum number of eight quad-rank DIMMs per cartridge. Plan the memory configurations using identical DIMMs to achieve the memory size target, taking into account that 64- and 128-DIMM count configurations result in the highest performance. Using a fourprocessor configuration as an example, do the following: • If the initial memory target is 64 GB, populate a four-processor system with eight cartridges of four 2- GB DIMMs each for a total of 32 DIMMs. • For 4-GB DIMMs, the initial memory target is 128-GB using 32 DIMMs. The maximum expansion target is 256 GB with 64 DIMMs. • For 8-GB DIMMs, the initial memory target is 256-GB using 32 DIMMs. The maximum expansion target is 512 GB with 64 DIMMs. • The maximum system memory capability is achieved with an initial memory target of 512 GB with 32 x 16-GB DIMMs and 1 TB with 64 x 16-GB DIMMs. For an eight-processor configuration, the same example applies, but must be done for both processor memory drawers, resulting a doubling of the memory capacity, and a 2 TB maximum with 128 x 16 GB DIMMs. Memory RAS The server supports the following AMP modes: • Advanced ECC memory mode provides the greatest memory capacity for a given DIMM size and provides x4 and x8 SDDC. This mode is the default option for this server. For more information, see "Advanced ECC memory population guidelines (on page 46)." • Online Spare memory mode provides protection against persistent DRAM failure. Rank-sparing is more efficient than DIMM-sparing since only a portion of a DIMM is set aside for memory protection. For more information, see "Online Spare memory population guidelines (on page 46)." • Mirrored Memory mode provides the maximum protection against failed DIMMs. Uncorrectable errors in the DIMMs of one memory cartridge are corrected by the DIMMs in the mirrored cartridge. The two memory controllers of each processor form a mirrored pair using two memory cartridges. For more information, see "Mirrored Memory population guidelines (on page 47)." Hardware options installation 45

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Hardware options installation 45
•
The largest contributor to maximum memory bandwidth performance is to use both memory
controllers inside the processor. To achieve maximum memory bandwidth performance, populate
both memory cartridges for each installed processor. This configuration is required for this server.
•
The second largest contributor to performance is to populate each DDR3 channel in each memory
cartridge. To achieve this, the minimum DIMM count per cartridge is four DIMMs installed in DIMM
pair locations A and B.
•
The next largest contributor to performance is the number of ranks per DIMM. Dual-rank DIMMs
perform significantly better than single-rank DIMMs. Quad-rank DIMMs offer a further performance
boost.
•
The best performance is obtained when all installed processors are enabled for Hemisphere mode.
Hemisphere mode is optimum when four or eight DIMMs are installed per cartridge. Hemisphere
mode can be achieved with two or six DIMMs per cartridge (2 cartridges per processor), but this
configuration is not optimal for Hemisphere mode. Hemisphere mode is required for this server.
•
Maximum throughput is achieved when all memory cartridges are fully populated with the maximum
number of eight quad-rank DIMMs per cartridge.
Plan the memory configurations using identical DIMMs to achieve the memory size target, taking into
account that 64- and 128-DIMM count configurations result in the highest performance. Using a four-
processor configuration as an example, do the following:
•
If the initial memory target is 64 GB, populate a four-processor system with eight cartridges of four 2-
GB DIMMs each for a total of 32 DIMMs.
•
For 4-GB DIMMs, the initial memory target is 128-GB using 32 DIMMs. The maximum expansion
target is 256 GB with 64 DIMMs.
•
For 8-GB DIMMs, the initial memory target is 256-GB using 32 DIMMs. The maximum expansion
target is 512 GB with 64 DIMMs.
•
The maximum system memory capability is achieved with an initial memory target of 512 GB with
32 x 16-GB DIMMs and 1 TB with 64 x 16-GB DIMMs.
For an eight-processor configuration, the same example applies, but must be done for both processor
memory drawers, resulting a doubling of the memory capacity, and a 2 TB maximum with 128 x 16 GB
DIMMs.
Memory RAS
The server supports the following AMP modes:
•
Advanced ECC memory mode provides the greatest memory capacity for a given DIMM size and
provides x4 and x8 SDDC. This mode is the default option for this server. For more information, see
"Advanced ECC memory population guidelines (on page
46
)."
•
Online Spare memory mode provides protection against persistent DRAM failure. Rank-sparing is
more efficient than DIMM-sparing since only a portion of a DIMM is set aside for memory protection.
For more information, see "Online Spare memory population guidelines (on page
46
)."
•
Mirrored Memory mode provides the maximum protection against failed DIMMs. Uncorrectable
errors in the DIMMs of one memory cartridge are corrected by the DIMMs in the mirrored cartridge.
The two memory controllers of each processor form a mirrored pair using two memory cartridges.
For more information, see "Mirrored Memory population guidelines (on page
47
)."