IBM DTLA-305040 Hard Drive Specifications - Page 114

DMA commands, Device/Head registers.

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11.4 DMA commands DMA commands are Ÿ Read DMA Ÿ Write DMA Data transfers using DMA commands differ in two ways from PIO transfers: Ÿ data transfers are performed using the slave DMA channel Ÿ no intermediate sector interrupts are issued on multisector commands Initiation of the DMA transfer commands is identical to the Read Sector or Write Sector commands except that the host initializes the slave-DMA channel prior to issuing the command. The interrupt handler for DMA transfers is different for the following reasons: Ÿ no intermediate sector interrupts are issued on multisector commands Ÿ the host resets the DMA channel prior to reading status from the device The DMA protocol allows high performance multitasking operating systems to eliminate processor overhead associated with PIO transfers. 1. Host initializes the slave DMA channel 2. Host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder and Device/Head registers. 3. Host writes command code to the Command Register 4. The device sets DMARQ when it is ready to transfer any part of the data. 5. Host transfers the data using the DMA transfer protocol currently in effect. 6. When all of the data has been transferred, the device generates an interrupt to the host. 7. Host resets the slave DMA channel. 8. Host reads the Status Register and, optionally, the Error Register. Deskstar 40GV & 75GXP hard disk drive specifications 102

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11.4 DMA commands
DMA commands are
°
Read DMA
°
Write DMA
Data transfers using DMA commands differ in two ways from PIO transfers:
°
data transfers are performed using the slave DMA channel
°
no intermediate sector interrupts are issued on multisector commands
Initiation of the DMA transfer commands is identical to the Read Sector or Write Sector commands
except that the host initializes the slave-DMA channel prior to issuing the command.
The interrupt handler for DMA transfers is different for the following reasons:
°
no intermediate sector interrupts are issued on multisector commands
°
the host resets the DMA channel prior to reading status from the device
The DMA protocol allows high performance multitasking operating systems to eliminate processor over-
head associated with PIO transfers.
1.
Host initializes the slave DMA channel
2.
Host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder and
Device/Head registers.
3.
Host writes command code to the Command Register
4.
The device sets DMARQ when it is ready to transfer any part of the data.
5.
Host transfers the data using the DMA transfer protocol currently in effect.
6.
When all of the data has been transferred, the device generates an interrupt to the host.
7.
Host resets the slave DMA channel.
8.
Host reads the Status Register and, optionally, the Error Register.
Deskstar 40GV & 75GXP hard disk drive specifications
102