Intel I3-530 Specifications - Page 12

Errata (Sheet 4 of 5) Number Steppings C-2 K-0 Status AAU77 X X No Fix AAU78 X X No Fix AAU79 X AAU80 X Fixed Fixed AAU82 X X No Fix AAU83 X X No Fix AAU84 X X No Fix AAU85 X X No Fix AAU86 X X No Fix AAU87 X X No Fix AAU88 X X No Fix AAU89 X X Plan Fix AAU90 X X No Fix AAU91 X X No Fix AAU92 X X No Fix AAU93 X Fixed AAU94 X Fixed AAU95 X Fixed AAU96 X X No Fix AAU97 X X No Fix AAU98 X X No Fix AAU99 X X No Fix AAU100 X X No Fix AAU101 X Fixed AAU102 X X No Fix AAU103 X X No Fix ERRATA 2MB Page Split Lock Accesses Combined With Complex Internal Events May Cause Unpredictable System Behavior If the APIC timer Divide Configuration Register (Offset 03E0H) is written at the same time that the APIC timer Current Count Register (Offset 0390H) reads 1H, it is possible that the APIC timer will deliver two interrupts. TXT.PUBLIC.KEY is Not Reliable 8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides With Interrupt Acknowledge Cycle From the Preceding Interrupt The APIC Timer Current Count Register May Prematurely Read 0x0 While the Timer is Still Running Secondary PCIe Port May Not Train After A Warm Reset The PECI Bus May Be Tri-stated after System Reset The Combination of a Page-Split Lock Access And Data Accesses That Are Split Across Cacheline Boundaries May Lead to Processor Livelock Processor Hangs on Package C6 State Exit A Synchronous SMI May be Delayed FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64bit Mode PCI Express x16 Port Links May Fail to Dynamically Switch From 5.0GT/s to 2.5GT/s PCI Express Cards May Not Train to x16 Link Width Unexpected Graphics VID Transition During Warm Reset May Cause the System to Hang IO_SMI Indication in SMRAM State Save Area May Be Lost VM Entry to 64-Bit Mode May Fail if Bits 48 And 47 of Guest RIP Are Different VM Entry Loading an Unusable SS Might Not Set SS.B to 1 FSW May Be Corrupted If an x87 Store Instruction Causes a Page Fault in VMX Non-Root Operation Under Certain Low Temperature Conditions, Some Uncore Performance Monitoring Events May Report Incorrect Results CKE May go Low Within tRFC(min) After a PD Exit Erratum AAU98 added to this specification Update in error; all erratum details removed from the specification update document. Performance Monitor Events for Hardware Prefetches Which Miss The L1 Data Cache May be Over-Counted VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] Correctable and Uncorrectable Cache Errors May be Reported Until the First Core C6 Transition Accesses to a VMCS May Not Operate Correctly If CR0.CD is Set on Any Logical Processor of a Core PCIe Port's LTSSM May Not Transition Properly in the Presence of TS1 or TS2 Ordered Sets That Have Unexpected Symbols Within those Sets 12 Specification Update