Intel I3-530 Specifications - Page 27

Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode

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AAU33. Delivery of Certain Events Immediately Following a VM Exit May Push a Corrupted RIP onto the Stack Problem: If any of the following events is delivered immediately following a VM exit to 64-bit mode from outside 64-bit mode, bits 63:32 of the RIP value pushed on the stack may be cleared to 0: • A non-maskable interrupt (NMI); • A machine-check exception (#MC); • A page fault (#PF) during instruction fetch; or • A general-protection exception (#GP) due to an attempt to decode an instruction whose length is greater than 15 bytes. Implication: Unexpected behavior may occur due to the incorrect value of the RIP on the stack. Specifically, return from the event handler via IRET may encounter an unexpected page fault or may begin fetching from an unexpected code address. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AAU34. Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is Received while All Cores in C6 Problem: If all logical processors in a core are in C6, an ExtINT delivery mode interrupt is pending in the xAPIC and interrupts are blocked with EFLAGS.IF=0, the interrupt will be processed after C6 wakeup and after interrupts are re-enabled (EFLAGS.IF=1). However, the pending interrupt event will not be cleared. Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the external interrupt. Intel has not observed this erratum with any commercially-available software/system. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAU35. Two xAPIC Timer Event Interrupts May Unexpectedly Occur Problem: If an xAPIC timer event is enabled and while counting down the current count reaches 1 at the same time that the processor thread begins a transition to a low power Cstate, the xAPIC may generate two interrupts instead of the expected one when the processor returns to C0. Implication: Due to this erratum, two interrupts may unexpectedly be generated by an xAPIC timer event. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 27 Specification Update

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27
Specification Update
AAU33.
Delivery of Certain Events Immediately Following a VM Exit May Push
a Corrupted RIP onto the Stack
Problem:
If any of the following events is delivered immediately following a VM exit to 64-bit
mode from outside 64-bit mode, bits 63:32 of the RIP value pushed on the stack may
be cleared to 0:
•
A non-maskable interrupt (NMI);
•
A machine-check exception (#MC);
•
A page fault (#PF) during instruction fetch; or
•
A general-protection exception (#GP) due to an attempt to decode an instruction
whose length is greater than 15 bytes.
Implication:
Unexpected behavior may occur due to the incorrect value of the RIP on the stack.
Specifically, return from the event handler via IRET may encounter an unexpected page
fault or may begin fetching from an unexpected code address.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU34.
Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode
Interrupt is Received while All Cores in C6
Problem:
If all logical processors in a core are in C6, an ExtINT delivery mode interrupt is
pending in the xAPIC and interrupts are blocked with EFLAGS.IF=0, the interrupt will
be processed after C6 wakeup and after interrupts are re-enabled (EFLAGS.IF=1).
However, the pending interrupt event will not be cleared.
Implication:
Due to this erratum, an infinite stream of interrupts will occur on the core servicing the
external interrupt. Intel has not observed this erratum with any commercially-available
software/system.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU35.
Two xAPIC Timer Event Interrupts May Unexpectedly Occur
Problem:
If an xAPIC timer event is enabled and while counting down the current count reaches
1 at the same time that the processor thread begins a transition to a low power C-
state, the xAPIC may generate two interrupts instead of the expected one when the
processor returns to C0.
Implication:
Due to this erratum, two interrupts may unexpectedly be generated by an xAPIC timer
event.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.