Intel I3-530 Specifications - Page 39

Logical Processor May Use Incorrect VPID after VM Entry That Returns

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AAU72. Logical Processor May Use Incorrect VPID after VM Entry That Returns From SMM Problem: A logical processor in VMX root operation should use VPID 0000H. Due to this erratum, a logical processor may instead use VPID 1FB3H if VMX root operation was entered using a VM entry that returns from SMM. Implication: After a VM entry that sets the "enable VPID" VM-execution control and that establishes VPID 1FB3H, the logical processor may erroneously use TLB entries that were cached in VMX root operation. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AAU73. The Memory Controller May Hang Due to Uncorrectable ECC Errors or Parity Errors Occurring on Both Channels in Mirror Channel Mode Problem: If an uncorrectable ECC or parity error occurs on the mirrored channel before an uncorrectable ECC or parity error on the other channel can be resolved, the Memory Controller may hang without an uncorrectable ECC or parity error being logged. Implication: The processor may hang and not report the error when uncorrectable ECC or parity errors occur in close proximity on both channels in a mirrored channel pair. No uncorrectable ECC or parity error will be logged in the machine check banks. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAU74. MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Problem: MSR_TURBO_RATIO_LIMIT MSR (1ADH) is designed to describe the maximum Intel Turbo Boost Technology potential of the processor. On some processors, a non-zero Intel Turbo Boost Technology value will be returned for non-existent core configurations. Implication: Due to this erratum, software using the MSR_TURBO_RATIO_LIMIT MSR to report Intel Turbo Boost Technology processor capabilities may report erroneous results. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AAU75. Internal Parity Error May Be Incorrectly Signaled during C6 Exit Problem: In a complex set of internal conditions an internal parity error may occur during a Core C6 exit. Implication: Due to this erratum, an uncorrected error may be reported and a machine check exception may be triggered. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 39 Specification Update

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39
Specification Update
AAU72.
Logical Processor May Use Incorrect VPID after VM Entry That Returns
From SMM
Problem:
A logical processor in VMX root operation should use VPID 0000H. Due to this erratum,
a logical processor may instead use VPID 1FB3H if VMX root operation was entered
using a VM entry that returns from SMM.
Implication:
After a VM entry that sets the "enable VPID" VM-execution control and that establishes
VPID 1FB3H, the logical processor may erroneously use TLB entries that were cached in
VMX root operation.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU73.
The Memory Controller May Hang Due to Uncorrectable ECC Errors or
Parity Errors Occurring on Both Channels in Mirror Channel Mode
Problem:
If an uncorrectable ECC or parity error occurs on the mirrored channel before an
uncorrectable ECC or parity error on the other channel can be resolved, the Memory
Controller may hang without an uncorrectable ECC or parity error being logged.
Implication:
The processor may hang and not report the error when uncorrectable ECC or parity
errors occur in close proximity on both channels in a mirrored channel pair. No
uncorrectable ECC or parity error will be logged in the machine check banks.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU74.
MSR_TURBO_RATIO_LIMIT MSR May Return Intel
®
Turbo Boost
Technology Core Ratio Multipliers for Non-Existent Core
Configurations
Problem:
MSR_TURBO_RATIO_LIMIT MSR (1ADH) is designed to describe the maximum Intel
Turbo Boost Technology potential of the processor. On some processors, a non-zero
Intel Turbo Boost Technology value will be returned for non-existent core
configurations.
Implication:
Due to this erratum, software using the MSR_TURBO_RATIO_LIMIT MSR to report Intel
Turbo Boost Technology processor capabilities may report erroneous results.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU75.
Internal Parity Error May Be Incorrectly Signaled during C6 Exit
Problem:
In a complex set of internal conditions an internal parity error may occur during a Core
C6 exit.
Implication:
Due to this erratum, an uncorrected error may be reported and a machine check
exception may be triggered.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.