Intel I3-530 Specifications - Page 47

VM Entry May Omit Consistency Checks Related to Bit 14 BS of

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AAU104. NTB/RP Link Will Send Extra TS2 Ordered Set During Link Training Problem: The NTB (Non-Transparent Bridge) when operating in NTB/RP (Root Port) mode will send a superfluous TS2 ordered set after transitioning to the CONFIGURATION.IDLE state during link training. This TS2 ordered set may contain invalid capability data. Implication: NTB/RP Link will transmit a TS2 ordered set after transitioning to the CONFIGURATION.IDLE state. No impact expected for specification compliant PCIe partners. Specification compliant PCIe link partners will have transitioned to CONFIGURATION.IDLE before this ordered set is sent and will ignore it. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAU105. PCIe Ports May Not Enter Slave Loopback Mode From the Configuration LTSSM State Problem: If a PCIe port's LTSSM (Link Training State Machine) is in the CONFIG.LINK_WIDTH_START state, it may not enter slave loopback mode when requested to do so by the link partner. If the request is missed the link will continue to train and enter the Slave loopback mode after it first transitions through the L0 and RECOVERY LTSSM states. Implication: Due to this erratum, PCIe ports may be delayed in entering the slave loopback mode. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAU106. USB Devices May Not Function Properly With Integrated Graphics While Running Targeted Stress Graphics Workloads With NonMatching Memory Configurations Problem: When the integrated graphics engine continuously generates a large stream of writes to system memory, and Intel Flex Memory Technology is enabled, with a different amount of memory in each channel, the memory arbiter may temporarily stop servicing other device-initiated traffic. In some cases this can cause certain USB devices, such as keyboard and mouse, to become unresponsive. Intel has only observed this erratum with targeted stress content. This erratum is not seen when the platform is configured with single channel or dual channel symmetric memory and is not dependent on the memory frequency. Implication: Due to this erratum, certain USB devices may become unresponsive. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAU107. VM Entry May Omit Consistency Checks Related to Bit 14 (BS) of the Pending Debug Exception Field in Guest-State Area of the VMCS Problem: Section "Checks on Guest Non-Register State" of Volume 3B specifies consistency checks that VM entry should perform for bit 14 (BS, indicating a pending single-step exception) of the pending debug exception field in guest-state area of the VMCS. These checks enforce the consistency of that bit with other fields in the guest-state area. Due to this erratum, VM entry may fail to perform these checks. Implication: A logical processor may enter VMX non-root operation with a pending single-step debug exception that not consistent other register state; this may result in unexpected behavior. Intel has not observed this erratum with any commercially available software. Workaround: When using VMWRITE to write to a field in the guest-state area, software should ensure that the value written is consistent with the state of other guest-state fields. 47 Specification Update

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47
Specification Update
AAU104.
NTB/RP Link Will Send Extra TS2 Ordered Set During Link Training
Problem:
The NTB (Non-Transparent Bridge) when operating in NTB/RP (Root Port) mode will
send a superfluous TS2 ordered set after transitioning to the CONFIGURATION.IDLE
state during link training. This TS2 ordered set may contain invalid capability data.
Implication:
NTB/RP Link will transmit a TS2 ordered set after transitioning to the
CONFIGURATION.IDLE state. No impact expected for specification compliant PCIe
partners. Specification compliant PCIe link partners will have transitioned to
CONFIGURATION.IDLE before this ordered set is sent and will ignore it.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU105.
PCIe Ports May Not Enter Slave Loopback Mode From the
Configuration LTSSM State
Problem:
If
a
PCIe
port’s
LTSSM
(Link
Training
State
Machine)
is
in
the
CONFIG.LINK_WIDTH_START state, it may not enter slave loopback mode when
requested to do so by the link partner. If the request is missed the link will continue to
train and enter the Slave loopback mode after it first transitions through the L0 and
RECOVERY LTSSM states.
Implication:
Due to this erratum, PCIe ports may be delayed in entering the slave loopback mode.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU106.
USB Devices May Not Function Properly With Integrated Graphics
While Running Targeted Stress Graphics Workloads With Non-
Matching Memory Configurations
Problem:
When the integrated graphics engine continuously generates a large stream of writes to
system memory, and Intel Flex Memory Technology is enabled, with a different amount
of memory in each channel, the memory arbiter may temporarily stop servicing other
device-initiated traffic. In some cases this can cause certain USB devices, such as
keyboard and mouse, to become unresponsive. Intel has only observed this erratum
with targeted stress content. This erratum is not seen when the platform is configured
with single channel or dual channel symmetric memory and is not dependent on the
memory frequency.
Implication:
Due to this erratum, certain USB devices may become unresponsive.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU107.
VM Entry May Omit Consistency Checks Related to Bit 14 (BS) of the
Pending Debug Exception Field in Guest-State Area of the VMCS
Problem:
Section “Checks on Guest Non-Register State” of Volume 3B specifies consistency
checks that VM entry should perform for bit 14 (BS, indicating a pending single-step
exception) of the pending debug exception field in guest-state area of the VMCS. These
checks enforce the consistency of that bit with other fields in the guest-state area. Due
to this erratum, VM entry may fail to perform these checks.
Implication:
A logical processor may enter VMX non-root operation with a pending single-step
debug exception that not consistent other register state; this may result in unexpected
behavior. Intel has not observed this erratum with any commercially available software.
Workaround:
When using VMWRITE to write to a field in the guest-state area, software should ensure
that the value written is consistent with the state of other guest-state fields.