Intel I3-530 Specifications - Page 28

EOI Transaction May Not be Sent if Software Enters Core C6 During an

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AAU36. EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt Service Routine Problem: If core C6 is entered after the start of an interrupt service routine but before a write to the APIC EOI (End of Interrupt) register, and the core is woken up by an event other than a fixed interrupt source the core may drop the EOI transaction the next time APIC EOI register is written and further interrupts from the same or lower priority level will be blocked. Implication: EOI transactions and interrupts may be blocked when core C6 is used during interrupt service routines. Intel has not observed this erratum with any commercially-available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAU37. Problem: FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM In general, a PEBS record should be generated on the first count of the event after the counter has overflowed. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from counting during SMM (System Management Mode). Due to this erratum, if 1. A performance counter overflowed before an SMI 2. A PEBS record has not yet been generated because another count of the event has not occurred 3. The monitored event occurs during SMM then a PEBS record will be saved after the next RSM instruction. When FREEZE_WHILE_SMM is set, a PEBS should not be generated until the event occurs outside of SMM. Implication: A PEBS record may be saved after an RSM instruction due to the associated performance counter detecting the monitored event during SMM; even when FREEZE_WHILE_SMM is set. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAU38. APIC Error "Received Illegal Vector" May be Lost Problem: APIC (Advanced Programmable Interrupt Controller) may not update the ESR (Error Status Register) flag Received Illegal Vector bit [6] properly when an illegal vector error is received on the same internal clock that the ESR is being written (as part of the write-read ESR access flow). The corresponding error interrupt will also not be generated for this case. Implication: Due to this erratum, an incoming illegal vector error may not be logged into ESR properly and may not generate an error interrupt. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 28 Specification Update

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28
Specification Update
AAU36.
EOI Transaction May Not be Sent if Software Enters Core C6 During an
Interrupt Service Routine
Problem:
If core C6 is entered after the start of an interrupt service routine but before a write to
the APIC EOI (End of Interrupt) register, and the core is woken up by an event other
than a fixed interrupt source the core may drop the EOI transaction the next time APIC
EOI register is written and further interrupts from the same or lower priority level will
be blocked.
Implication:
EOI transactions and interrupts may be blocked when core C6 is used during interrupt
service routines. Intel has not observed this erratum with any commercially-available
software.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU37.
FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS
During SMM
Problem:
In general, a PEBS record should be generated on the first count of the event after the
counter has overflowed. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR
1D9H, bit [14]) prevents performance counters from counting during SMM (System
Management Mode). Due to this erratum, if
1.
A performance counter overflowed before an SMI
2.
A PEBS record has not yet been generated because another count of the event has
not occurred
3.
The monitored event occurs during SMM
then a PEBS record will be saved after the next RSM instruction.
When FREEZE_WHILE_SMM is set, a PEBS should not be generated until the event
occurs outside of SMM.
Implication:
A PEBS record may be saved after an RSM instruction due to the associated
performance counter detecting the monitored event during SMM; even when
FREEZE_WHILE_SMM is set.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU38.
APIC Error “Received Illegal Vector” May be Lost
Problem:
APIC (Advanced Programmable Interrupt Controller) may not update the ESR (Error
Status Register) flag Received Illegal Vector bit [6] properly when an illegal vector error
is received on the same internal clock that the ESR is being written (as part of the
write-read ESR access flow). The corresponding error interrupt will also not be
generated for this case.
Implication:
Due to this erratum, an incoming illegal vector error may not be logged into ESR
properly and may not generate an error interrupt.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.