Intel I3-530 Specifications - Page 41

Virtual Wire B Mode Interrupt May Be Dropped When it Collides - dual core

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AAU80. 8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides With Interrupt Acknowledge Cycle From the Preceding Interrupt Problem: If an un-serviced 8259 Virtual Wire B Mode (8259 connected to IOAPIC) External Interrupt is pending in the APIC and a second 8259 Virtual Wire B Mode External Interrupt arrives, the processor may incorrectly drop the second 8259 Virtual Wire B Mode External Interrupt request. This occurs when both the new External Interrupt and Interrupt Acknowledge for the previous External Interrupt arrive at the APIC at the same time. Implication: to this erratum, any further 8259 Virtual Wire B Mode External Interrupts will subsequently be ignored. Workaround: Do not use 8259 Virtual Wire B mode when using the 8259 to deliver interrupts. Status: For the steppings affected, see the Summary Tables of Changes. AAU82. The APIC Timer Current Count Register May Prematurely Read 0x0 While the Timer is Still Running Problem: The APIC Timer Current Counter Register may prematurely read 0x00000000 while the timer is still running. This problem occurs when a core frequency or C-state transition occurs while the APIC timer countdown is in progress. Implication: Due to this erratum, certain software may incorrectly assess that the APIC timer countdown is complete when it is actually still running. This erratum does not affect the delivery of the timer interrupt. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AAU83. Secondary PCIe Port May Not Train After A Warm Reset Problem: In a dual PCIe port configuration, the secondary PCIe port may not train after a warm reset. Implication: The second PCIe port and therefore any device connected to the PCIe bus instantiated by that PCIe port may not be functional after a warm reset. Intel has not observed this erratum with any commercially available system. Workaround: A BIOS code change has been identified and may be implemented as a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 41 Specification Update

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41
Specification Update
AAU80.
8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides
With Interrupt Acknowledge Cycle From the Preceding Interrupt
Problem:
If an un-serviced 8259 Virtual Wire B Mode (8259 connected to IOAPIC) External
Interrupt is pending in the APIC and a second 8259 Virtual Wire B Mode External
Interrupt arrives, the processor may incorrectly drop the second 8259 Virtual Wire B
Mode External Interrupt request. This occurs when both the new External Interrupt and
Interrupt Acknowledge for the previous External Interrupt arrive at the APIC at the
same time.
Implication:
to this erratum, any further 8259 Virtual Wire B Mode External Interrupts will
subsequently be ignored.
Workaround:
Do not use 8259 Virtual Wire B mode when using the 8259 to deliver interrupts.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU82.
The APIC Timer Current Count Register May Prematurely Read 0x0
While the Timer is Still Running
Problem:
The APIC Timer Current Counter Register may prematurely read 0x00000000 while the
timer is still running. This problem occurs when a core frequency or C-state transition
occurs while the APIC timer countdown is in progress.
Implication:
Due to this erratum, certain software may incorrectly assess that the APIC timer
countdown is complete when it is actually still running. This erratum does not affect the
delivery of the timer interrupt.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAU83.
Secondary PCIe Port May Not Train After A Warm Reset
Problem:
In a dual PCIe port configuration, the secondary PCIe port may not train after a warm
reset.
Implication:
The second PCIe port and therefore any device connected to the PCIe bus instantiated
by that PCIe port may not be functional after a warm reset. Intel has not observed this
erratum with any commercially available system.
Workaround:
A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.