Intel I3-530 Specifications - Page 46

Implication: All fixed-function performance counters will be disabled after an affected VM exit, even if the VM exit should have enabled them based on the IA32_PERF_GLOBAL_CTRL field in the guest-state area of the VMCS. Workaround: A VM monitor that wants the fixed-function performance counters to be enabled after a VM exit may do one of two things: (1) clear the "load IA32_PERF_GLOBAL_CTRL" VM- exit control; or (2) include an entry for the IA32_PERF_GLOBAL_CTRL MSR in the VMexit MSR-load list. Status: For the steppings affected, see the Summary Tables of Changes. AAU101. Correctable and Uncorrectable Cache Errors May be Reported Until the First Core C6 Transition Problem: On a subset of processors it is possible that correctable/uncorrectable cache errors may be logged and/or a machine check exception may occur prior to the first core C6 transition. The errors will be logged in IA32_MC5_STATUS MSR (415H) with the MCACOD (Machine Check Architecture Error Code) bits [15:0] indicating a Cache Hierarchy Error of the form 000F 0001 RRRR TTLL. Implication: Due to this erratum, correctable/uncorrectable cache error may be logged or signaled. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AAU102. Accesses to a VMCS May Not Operate Correctly If CR0.CD is Set on Any Logical Processor of a Core Problem: The VMX (virtual-machine extensions) are controlled by the VMCS (virtual-machine control structure). If CR0.CD is set on any logical processor of a core, operations using the VMCS may not function correctly. Such operations include the VMREAD and VMWRITE instructions as well as VM entries and VM exits. Implication: If CR0.CD is set on either logical processor in a core, the VMWRITE instruction may not correctly update the VMCS and the VMREAD instruction may not return correct data. VM entries may not load state properly and may not establish VMX controls properly. VM exits may not save or load state properly. Workaround: VMMs (Virtual-machine monitors) should ensure that CR0.CD is clear on all logical processors of a core before entering VMX operation on any logical processor. Software should not set CR0.CD on a logical processor if any logical processor of the same core is in VMX operation. VMM software should prevent guest software from setting CR0.CD by setting bit 30 in the CR0 guest/host mask field in every VMCS. Status: For the steppings affected, see the Summary Tables of Changes. AAU103. PCIe Port's LTSSM May Not Transition Properly in the Presence of TS1 or TS2 Ordered Sets That Have Unexpected Symbols Within those Sets Problem: When a PCIe port receives TS1 and/or TS2 ordered sets with unexpected symbols (per the PCIe Base Specification), the port's LTSSM (Link Training State Machine) might not transition according to the PCIe Base Specification requirements. The LTSSM may incorrectly stay in its current state, or transition to an incorrect state. If the unexpected symbols are sporadic in nature the link will recover and go to the proper state. Implication: PCIe Port's LTSMM may not transition according to PCIe Base Specification as described above. This problem has not been seen in real system testing, but was discovered by synthetic tests designed to check for illegal conditions. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 46 Specification Update