Intel I3-530 Specifications - Page 43

AAU88. FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode Problem: The FP (Floating Point) Data Operand Pointer is the effective address of the operand associated with the last non-control FP instruction executed by the processor. If an 80bit FP access (load or store) uses a 32-bit address size in 64-bit mode and the memory access wraps a 4-Gbyte boundary and the FP environment is subsequently saved, the value contained in the FP Data Operand Pointer may be incorrect. Implication: Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-bit FP load around a 4-Gbyte boundary in this way is not a normal programming practice. Intel has not observed this erratum with any commercially available software. Workaround: If the FP Data Operand Pointer is used in a 64-bit operating system which may run code accessing 32-bit addresses, care must be taken to ensure that no 80-bit FP accesses are wrapped around a 4-Gbyte boundary. Status: For the steppings affected, see the Summary Tables of Changes. AAU89. PCI Express x16 Port Links May Fail to Dynamically Switch From 5.0GT/s to 2.5GT/s Problem: If an endpoint device initiates a PCI Express speed change from 5.0 GT/s to 2.5 GT/s, the link may incorrectly go into Recovery.Idle rather than the expected Recovery.Speed state. This may cause the link to lose sync, eventually resulting in a link down. The link will recover and re-train to the L0 state, however any outstanding packets queued during the speed change may be lost. Implication: Due to this erratum, the link may lose sync resulting in link down with queued packet being lost. No known failures have been observed on systems using production PCI Express graphics cards. This erratum has only been observed in a synthetic test environment. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAU90. PCI Express Cards May Not Train to x16 Link Width Problem: The Maximum Link Width field in the Link Capabilities register (LCAP; Bus 0; Device 1; Function 0; offset 0xAC; bits [9:4]) may limit the width of the PCI Express link to x8, even though the processor may actually be capable of supporting the full x16 width. Implication: PCI Express x16 Graphics Cards used in normal operation and PCI Express CLB (Compliance Load Board) Cards used during PCI Express Compliance mode testing may only train to x8 link width. Workaround: A BIOS code change has been identified and may be implemented as a workaround for this erratum Status: For the steppings affected, see the Summary Tables of Changes. AAU91. Unexpected Graphics VID Transition During Warm Reset May Cause the System to Hang Problem: During a warm reset to the processor, the graphics VID (Voltage ID) may transition to an unexpected value that may cause the voltage regulator to shut off. Implication: The processor may hang during integrated graphics initialization. Cold boots and platforms using discrete graphics are not affected by this issue. Workaround: A BIOS code change has been identified and may be implemented as a workaround for this erratum. 43 Specification Update