Intel I3-530 Specifications - Page 23

AAU20. A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as Armed Problem: A processor write to the address range armed by the MONITOR instruction may not immediately trigger the monitoring hardware. Consequently, a VM exit on a later MWAIT may incorrectly report the monitoring hardware as armed, when it should be reported as unarmed due to the write occurring prior to the MWAIT. Implication: If a write to the range armed by the MONITOR instruction occurs between the MONITOR and the MWAIT, the MWAIT instruction may start executing before the monitoring hardware is triggered. If the MWAIT instruction causes a VM exit, this could cause its exit qualification to incorrectly report 0x1. In the recommended usage model for MONITOR/MWAIT, there is no write to the range armed by the MONITOR instruction between the MONITOR and the MWAIT. Workaround: Software should never write to the address range armed by the MONITOR instruction between the MONITOR and the subsequent MWAIT. Status: For the steppings affected, see the Summary Tables of Changes. AAU21. Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately Problem: The performance monitor event SEGMENT_REG_LOADS (Event 06H) counts instructions that load new values into segment registers. The value of the count may be inaccurate. Implication: The performance monitor event SEGMENT_REG_LOADS may reflect a count higher or lower than the actual number of events. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAU22. #GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code Problem: During a #GP (General Protection Exception), the processor pushes an error code on to the exception handler's stack. If the segment selector descriptor straddles the canonical boundary, the error code pushed onto the stack may be incorrect. Status: An incorrect error code may be pushed onto the stack. Intel has not observed this erratum with any commercially-available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAU23. Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint is Set on a #GP Instruction Problem: While coming out of cold reset or exiting from C6, if the processor encounters an instruction longer than 15 bytes (which causes a #GP) and a code breakpoint is enabled on that instruction, an IQ (Instruction Queue) parity error may be incorrectly logged resulting in an MCE (Machine Check Exception). Implication: When this erratum occurs, an MCE may be incorrectly signaled. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 23 Specification Update