Intel S975XBX2 Product Specification - Page 53

Technical Reference 2.6 PCI Conventional Interrupt Routing Map This section describes interrupt sharing and how the interrupt signals are connected between the PCI Conventional bus connectors and onboard PCI Conventional devices. The PCI Conventional specification describes how interrupts can be shared between devices attached to the PCI Conventional bus. In most cases, the small amount of latency added by interrupt sharing does not affect the operation or throughput of the devices. In some special cases where maximum performance is needed from a device, a PCI Conventional device should not share an interrupt with other PCI Conventional devices. Use the following information to avoid sharing an interrupt with a PCI Conventional add-in card. PCI Conventional devices are categorized as follows to specify their interrupt grouping: • INTA: By default, all add-in cards that require only one interrupt are in this category. For almost all cards that require more than one interrupt, the first interrupt on the card is also classified as INTA. • INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is classified as INTB. (This is not an absolute requirement.) • INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a fourth interrupt is classified as INTD. The ICH7-R/ICH7-DH has eight Programmable Interrupt Request (PIRQ) input signals. All PCI Conventional interrupt sources either onboard or from a PCI Conventional add-in card connect to one of these PIRQ signals. Some PCI Conventional interrupt sources are electrically tied together on the board and therefore share the same interrupt. Table 15 shows an example of how the PIRQ signals are routed. Table 15. PCI Interrupt Routing Map PCI Interrupt Source PCI bus connector 1 PCI bus connector 2 IEEE-1394a controller Discrete SATA Controller ICH7-R/ICH7-DH PIRQ Signal Name PIRQA PIRQB PIRQC PIRQD PIRQE PIRQF PIRQG PIRQH INTD INTA INTB INTC INTD INTC INTA INTB INTA INTA NOTE In PIC mode, the ICH7-R/ICH7-DH can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in certain interruptconstrained situations, it is possible for two or more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 14 for the allocation of PIRQ lines to IRQ signals in APIC mode. PCI interrupt assignments to the USB ports, Serial ATA ports, and PCI Express ports are dynamic. 53